Kersi H. Vakil

Person

Olympia, WA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Transmitters providing cycle encoded signals
- Patent number 8,559,530
- Issue date Oct 15, 2013
- Intel Corporation
- Jerry G. Jex
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Receivers for cycle encoded signals
- Patent number 8,149,928
- Issue date Apr 3, 2012
- Intel Corporation
- Jed D. Griffin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Training pattern for a biased clock recovery tracking loop
- Patent number 8,098,783
- Issue date Jan 17, 2012
- Intel Corporation
- Adarsh Panikkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Receivers for cycle encoded signals
- Patent number 7,720,159
- Issue date May 18, 2010
- Intel Corporation
- Jed D. Griffin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Dual clock domain deskew circuit
- Patent number 7,656,983
- Issue date Feb 2, 2010
- Intel Corporation
- Daniel S. Klowden
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Various methods and apparatuses for lane to lane deskewing
- Patent number 7,466,723
- Issue date Dec 16, 2008
- Intel Corporation
- Kersi H. Vakil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Training pattern for a biased clock recovery tracking loop
- Patent number 7,369,634
- Issue date May 6, 2008
- Intel Corporation
- Adarsh Panikkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Transmitters providing cycle encoded signals
- Patent number 7,308,025
- Issue date Dec 11, 2007
- Intel Corporation
- Jerry G Jex
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Receivers for cycle encoded signals
- Patent number 7,305,023
- Issue date Dec 4, 2007
- Intel Corporation
- Jed D. Griffin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Adaptive throughput pulse width modulation communication scheme
- Patent number 7,050,507
- Issue date May 23, 2006
- Intel Corporation
- Kersi H. Vakil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interpolator testing system
- Patent number 7,043,392
- Issue date May 9, 2006
- Intel Corporation
- Kersi H. Vakil
- G11 - INFORMATION STORAGE
Information Patent Grant
Leakage testing for differential signal transceiver
- Patent number 7,019,550
- Issue date Mar 28, 2006
- Intel Corporation
- Eric R. Wehage
- G01 - MEASURING TESTING
Information Patent Grant
Interpolator linearity testing system
- Patent number 7,009,431
- Issue date Mar 7, 2006
- Intel Corporation
- Adarsh Panikkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Point to point alternating current (AC) impedance compensation for...
- Patent number 6,549,031
- Issue date Apr 15, 2003
- Intel Corporation
- Jerry G. Jex
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Low skew minimized clock splitter
- Patent number 6,466,074
- Issue date Oct 15, 2002
- Intel Corporation
- Kersi H. Vakil
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
RECEIVERS FOR CYCLE ENCODED SIGNALS
- Publication number 20100226419
- Publication date Sep 9, 2010
- Jed D. Griffin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
TRAINING PATTERN FOR A BIASED CLOCK RECOVERY TRACKING LOOP
- Publication number 20080260082
- Publication date Oct 23, 2008
- Adarsh Panikkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Selective tracking of serial communication link data
- Publication number 20080130815
- Publication date Jun 5, 2008
- S. Reji Kumar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TRANSMITTERS PROVIDING CYCLE ENCODED SIGNALS
- Publication number 20080123722
- Publication date May 29, 2008
- Jerry G. Jex
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
RECEIVERS FOR CYCLE ENCODED SIGNALS
- Publication number 20080101505
- Publication date May 1, 2008
- Jed D. Griffin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Dual clock domain deskew circuit
- Publication number 20080080654
- Publication date Apr 3, 2008
- Daniel S. Klowden
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Input/output agent having multiple secondary ports
- Publication number 20070239906
- Publication date Oct 11, 2007
- Kersi H. Vakil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Training pattern for a biased clock recovery tracking loop
- Publication number 20060050822
- Publication date Mar 9, 2006
- Adarsh Panikkar
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Interpolator linearity testing system
- Publication number 20050285652
- Publication date Dec 29, 2005
- Adarsh Panikkar
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Various methods and apparatuses for lane to lane deskewing
- Publication number 20050286565
- Publication date Dec 29, 2005
- Kersi H. Vakil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Leakage testing for differential signal transceiver
- Publication number 20050285620
- Publication date Dec 29, 2005
- Eric R. Wehage
- G01 - MEASURING TESTING
Information Patent Application
Interpolator testing system
- Publication number 20050280452
- Publication date Dec 22, 2005
- Kersi H. Vakil
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
System and method for automatically calibrating two-tap and multi-t...
- Publication number 20050201454
- Publication date Sep 15, 2005
- Intel Corporation
- Santanu Chaudhuri
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Receivers for cycle encoded signals
- Publication number 20050018779
- Publication date Jan 27, 2005
- Jed D. Griffin
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Transmitters providing cycle encoded signals
- Publication number 20050018761
- Publication date Jan 27, 2005
- Jerry G. Jex
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Adaptive throughput pulse width modulation communication scheme
- Publication number 20030200364
- Publication date Oct 23, 2003
- Intel Corporation
- Kersi H. Vakil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOW SKEW MINIMIZED CLOCK SPLITTER
- Publication number 20020140488
- Publication date Oct 3, 2002
- Kersi H. Vakil
- G06 - COMPUTING CALCULATING COUNTING

Kersi H. Vakil

Person

Patents Grantslast 30 patents

Transmitters providing cycle encoded signals

Receivers for cycle encoded signals

Training pattern for a biased clock recovery tracking loop

Receivers for cycle encoded signals

Dual clock domain deskew circuit

Various methods and apparatuses for lane to lane deskewing

Training pattern for a biased clock recovery tracking loop

Transmitters providing cycle encoded signals

Receivers for cycle encoded signals

Adaptive throughput pulse width modulation communication scheme

Interpolator testing system

Leakage testing for differential signal transceiver

Interpolator linearity testing system

Point to point alternating current (AC) impedance compensation for...

Low skew minimized clock splitter

Patents Applicationslast 30 patents

RECEIVERS FOR CYCLE ENCODED SIGNALS

TRAINING PATTERN FOR A BIASED CLOCK RECOVERY TRACKING LOOP

Selective tracking of serial communication link data

TRANSMITTERS PROVIDING CYCLE ENCODED SIGNALS

RECEIVERS FOR CYCLE ENCODED SIGNALS

Dual clock domain deskew circuit

Input/output agent having multiple secondary ports

Training pattern for a biased clock recovery tracking loop

Interpolator linearity testing system

Various methods and apparatuses for lane to lane deskewing

Leakage testing for differential signal transceiver

Interpolator testing system

System and method for automatically calibrating two-tap and multi-t...

Receivers for cycle encoded signals

Transmitters providing cycle encoded signals

Adaptive throughput pulse width modulation communication scheme

LOW SKEW MINIMIZED CLOCK SPLITTER