Kerstin Ruttloff

Person

Hainichen, DE

People

Patents Grantslast 30 patents

Information Patent Grant
Multi-step deposition of a spacer material for reducing void format...
- Patent number 8,987,103
- Issue date Mar 24, 2015
- GLOBALFOUNDRIES Inc.
- Markus Lenski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Oxide deposition by using a double liner approach for reducing patt...
- Patent number 8,772,843
- Issue date Jul 8, 2014
- GLOBALFOUNDRIES Inc.
- Stephan Kronholz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sacrificial spacer approach for differential source/drain implantat...
- Patent number 8,709,902
- Issue date Apr 29, 2014
- GLOBALFOUNDRIES Inc.
- Thilo Scheiper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Threshold adjustment for MOS devices by adapting a spacer width pri...
- Patent number 8,440,534
- Issue date May 14, 2013
- Advanced Micro Devices, Inc.
- Uwe Griebenow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SOI semiconductor device comprising substrate diodes having a topog...
- Patent number 8,436,425
- Issue date May 7, 2013
- GLOBALFOUNDRIES Inc.
- Jens Heinrich
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Contacts and vias of a semiconductor device formed by a hard mask a...
- Patent number 8,318,598
- Issue date Nov 27, 2012
- Advanced Micro Devices, Inc.
- Sven Beyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Drive current adjustment for transistors by local gate engineering
- Patent number 8,188,871
- Issue date May 29, 2012
- Advanced Micro Devices, Inc.
- Manfred Horstmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of creating a strained channel region in a transistor by dee...
- Patent number 8,110,487
- Issue date Feb 7, 2012
- Advanced Micro Devices, Inc.
- Uwe Griebenow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etch stop layer of reduced thickness for patterning a dielectric ma...
- Patent number 8,097,542
- Issue date Jan 17, 2012
- GLOBALFOUNDRIES Inc.
- Karsten Wieczorek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SOI semiconductor device with reduced topography above a substrate...
- Patent number 8,048,726
- Issue date Nov 1, 2011
- GLOBALFOUNDRIES Inc.
- Jens Heinrich
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing defects of gate of CMOS devices during cleaning...
- Patent number 8,039,338
- Issue date Oct 18, 2011
- GLOBALFOUNDRIES Inc.
- Manfred Horstmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Enhanced cap layer integrity in a high-K metal gate stack by using...
- Patent number 7,981,740
- Issue date Jul 19, 2011
- GLOBALFOUNDRIES Inc.
- Markus Lenski
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Sacrificial Spacer Approach for Differential Source/Drain Implantat...
- Publication number 20120156837
- Publication date Jun 21, 2012
- GLOBALFOUNDRIES INC.
- Thilo Scheiper
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Oxide Deposition by Using a Double Liner Approach for Reducing Patt...
- Publication number 20120049296
- Publication date Mar 1, 2012
- GLOBALFOUNDRIES INC.
- Stephan Kronholz
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THRESHOLD ADJUSTMENT FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRI...
- Publication number 20110223732
- Publication date Sep 15, 2011
- Advanced Micro Devices, Inc.
- Uwe Griebenow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOI SEMICONDUCTOR DEVICE WITH REDUCED TOPOGRAPHY ABOVE A SUBSTRATE...
- Publication number 20110189825
- Publication date Aug 4, 2011
- Jens Heinrich
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOI SEMICONDUCTOR DEVICE COMPRISING SUBSTRATE DIODES HAVING A TOPOG...
- Publication number 20110186929
- Publication date Aug 4, 2011
- Jens Heinrich
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ENHANCED CAP LAYER INTEGRITY IN A HIGH-K METAL GATE STACK BY USING...
- Publication number 20100330757
- Publication date Dec 30, 2010
- Markus Lenski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-STEP DEPOSITION OF A SPACER MATERIAL FOR REDUCING VOID FORMAT...
- Publication number 20100289083
- Publication date Nov 18, 2010
- Markus Lenski
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONTACTS AND VIAS OF A SEMICONDUCTOR DEVICE FORMED BY A HARD MASK A...
- Publication number 20100078823
- Publication date Apr 1, 2010
- Sven Beyer
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRIVE CURRENT ADJUSTMENT FOR TRANSISTORS BY LOCAL GATE ENGINEERING
- Publication number 20100025776
- Publication date Feb 4, 2010
- Manfred Horstmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUE FOR REDUCING SILICIDE NON-UNIFORMITIES IN POLYSILICON GAT...
- Publication number 20100025782
- Publication date Feb 4, 2010
- Uwe Griebenow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Threshold adjustment for MOS devices by adapting a spacer width pri...
- Publication number 20090321850
- Publication date Dec 31, 2009
- Uwe Griebenow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRIVE CURRENT ADJUSTMENT FOR TRANSISTORS FORMED IN THE SAME ACTIVE...
- Publication number 20090294868
- Publication date Dec 3, 2009
- Uwe Griebenow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR REDUCING DEFECTS OF GATE OF CMOS DEVICES DURING CLEANING...
- Publication number 20090273036
- Publication date Nov 5, 2009
- Manfred Horstmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETCH STOP LAYER OF REDUCED THICKNESS FOR PATTERNING A DIELECTRIC MA...
- Publication number 20090218629
- Publication date Sep 3, 2009
- Karsten Wieczorek
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF CREATING A STRAINED CHANNEL REGION IN A TRANSISTOR BY DEE...
- Publication number 20090194789
- Publication date Aug 6, 2009
- Uwe Griebenow
- H01 - BASIC ELECTRIC ELEMENTS

Kerstin Ruttloff

Person

Patents Grantslast 30 patents

Multi-step deposition of a spacer material for reducing void format...

Oxide deposition by using a double liner approach for reducing patt...

Sacrificial spacer approach for differential source/drain implantat...

Threshold adjustment for MOS devices by adapting a spacer width pri...

SOI semiconductor device comprising substrate diodes having a topog...

Contacts and vias of a semiconductor device formed by a hard mask a...

Drive current adjustment for transistors by local gate engineering

Method of creating a strained channel region in a transistor by dee...

Etch stop layer of reduced thickness for patterning a dielectric ma...

SOI semiconductor device with reduced topography above a substrate...

Method for reducing defects of gate of CMOS devices during cleaning...

Enhanced cap layer integrity in a high-K metal gate stack by using...

Patents Applicationslast 30 patents

Sacrificial Spacer Approach for Differential Source/Drain Implantat...

Oxide Deposition by Using a Double Liner Approach for Reducing Patt...

THRESHOLD ADJUSTMENT FOR MOS DEVICES BY ADAPTING A SPACER WIDTH PRI...

SOI SEMICONDUCTOR DEVICE WITH REDUCED TOPOGRAPHY ABOVE A SUBSTRATE...

SOI SEMICONDUCTOR DEVICE COMPRISING SUBSTRATE DIODES HAVING A TOPOG...

ENHANCED CAP LAYER INTEGRITY IN A HIGH-K METAL GATE STACK BY USING...

MULTI-STEP DEPOSITION OF A SPACER MATERIAL FOR REDUCING VOID FORMAT...

CONTACTS AND VIAS OF A SEMICONDUCTOR DEVICE FORMED BY A HARD MASK A...

DRIVE CURRENT ADJUSTMENT FOR TRANSISTORS BY LOCAL GATE ENGINEERING

TECHNIQUE FOR REDUCING SILICIDE NON-UNIFORMITIES IN POLYSILICON GAT...

Threshold adjustment for MOS devices by adapting a spacer width pri...

DRIVE CURRENT ADJUSTMENT FOR TRANSISTORS FORMED IN THE SAME ACTIVE...

METHOD FOR REDUCING DEFECTS OF GATE OF CMOS DEVICES DURING CLEANING...

ETCH STOP LAYER OF REDUCED THICKNESS FOR PATTERNING A DIELECTRIC MA...

METHOD OF CREATING A STRAINED CHANNEL REGION IN A TRANSISTOR BY DEE...