Ket-Chong Yap

Person

San Ramon, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Configuration latch for programmable logic device
- Patent number 12,149,244
- Issue date Nov 19, 2024
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Grant
Area-efficient configuration latch for programmable logic device
- Patent number 11,935,618
- Issue date Mar 19, 2024
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Grant
Configuration latch for programmable logic device
- Patent number 11,848,671
- Issue date Dec 19, 2023
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic device with design for test functionality
- Patent number 11,848,066
- Issue date Dec 19, 2023
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Grant
Sectional configuration for programmable logic devices
- Patent number 11,652,486
- Issue date May 16, 2023
- QuickLogic Corporation
- Ket Chong Yap
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Switchable power islands having configurably on routing paths
- Patent number 10,148,270
- Issue date Dec 4, 2018
- QuickLogic Corporation
- Pinaki Chakrabarti
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adjustable interface buffer circuit between a programmable logic de...
- Patent number 8,487,652
- Issue date Jul 16, 2013
- QuickLogic Corporation
- Ket-Chong Yap
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
FPGA programming structure for ATPG test coverage
- Patent number 8,091,001
- Issue date Jan 3, 2012
- QuickLogic Corporation
- Stephen U. Yao
- G01 - MEASURING TESTING
Information Patent Grant
Adjustable interface buffer circuit between a programmable logic de...
- Patent number 8,018,248
- Issue date Sep 13, 2011
- QuickLogic Corporation
- Ket-Chong Yap
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Low power mode
- Patent number 7,646,216
- Issue date Jan 12, 2010
- QuickLogic Corporation
- Wilma Waiman Shiao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable antifuse interfacing a programmable logic and a dedica...
- Patent number 6,552,410
- Issue date Apr 22, 2003
- QuickLogic Corporation
- David D. Eaton
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Serializer/deserializer embedded in a programmable device
- Patent number 6,542,096
- Issue date Apr 1, 2003
- QuickLogic Corporation
- Andrew K. Chan
- G11 - INFORMATION STORAGE
Information Patent Grant
Precharge circuitry in RAM circuit
- Patent number 6,097,651
- Issue date Aug 1, 2000
- QuickLogic Corporation
- Andrew K. Chan
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE
- Publication number 20240171178
- Publication date May 23, 2024
- QuickLogic Corporation
- Ket Chong YAP
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH DESIGN FOR TEST FUNCTIONALITY
- Publication number 20240170087
- Publication date May 23, 2024
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Application
SECTIONAL CONFIGURATION FOR PROGRAMMABLE LOGIC DEVICES
- Publication number 20230353156
- Publication date Nov 2, 2023
- QuickLogic Corporation
- Ket Chong YAP
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
AREA-EFFICIENT CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE
- Publication number 20230343372
- Publication date Oct 26, 2023
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMABLE LOGIC DEVICE WITH DESIGN FOR TEST FUNCTIONALITY
- Publication number 20230317192
- Publication date Oct 5, 2023
- QuickLogic Corporation
- Ket Chong Yap
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE
- Publication number 20230299773
- Publication date Sep 21, 2023
- QuickLogic Corporation
- Ket Chong YAP
- G11 - INFORMATION STORAGE
Information Patent Application
SWITCHABLE POWER ISLANDS HAVING CONFIGURABLY ON ROUTING PATHS
- Publication number 20180269879
- Publication date Sep 20, 2018
- QuickLogic Corporation
- Pinaki CHAKRABARTI
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Adjustable Interface Buffer Circuit Between A Programmable Logic De...
- Publication number 20110298492
- Publication date Dec 8, 2011
- QuickLogic Corporation
- Ket-Chong Yap
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
FPGA Programming Structure for ATPG Test Coverage
- Publication number 20080133988
- Publication date Jun 5, 2008
- QuickLogic Corporation
- Stephen U. Yao
- G01 - MEASURING TESTING
Information Patent Application
Low Power Mode
- Publication number 20080122483
- Publication date May 29, 2008
- QuickLogic Corporation
- Wilma Waiman Shiao
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Adjustable interface buffer circuit between a programmable logic de...
- Publication number 20080074141
- Publication date Mar 27, 2008
- QuickLogic Corporation
- Ket-Chong Yap
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SERIALIZER/DESERIALIZER EMBEDDED IN A PROGRAMMABLE DEVICE
- Publication number 20030039168
- Publication date Feb 27, 2003
- QuickLogic Corporation
- Andrew K. Chan
- G11 - INFORMATION STORAGE

Ket-Chong Yap

Person

Patents Grantslast 30 patents

Configuration latch for programmable logic device

Area-efficient configuration latch for programmable logic device

Configuration latch for programmable logic device

Programmable logic device with design for test functionality

Sectional configuration for programmable logic devices

Switchable power islands having configurably on routing paths

Adjustable interface buffer circuit between a programmable logic de...

FPGA programming structure for ATPG test coverage

Adjustable interface buffer circuit between a programmable logic de...

Low power mode

Programmable antifuse interfacing a programmable logic and a dedica...

Serializer/deserializer embedded in a programmable device

Precharge circuitry in RAM circuit

Patents Applicationslast 30 patents

CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE

PROGRAMMABLE LOGIC DEVICE WITH DESIGN FOR TEST FUNCTIONALITY

SECTIONAL CONFIGURATION FOR PROGRAMMABLE LOGIC DEVICES

AREA-EFFICIENT CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE

PROGRAMMABLE LOGIC DEVICE WITH DESIGN FOR TEST FUNCTIONALITY

CONFIGURATION LATCH FOR PROGRAMMABLE LOGIC DEVICE

SWITCHABLE POWER ISLANDS HAVING CONFIGURABLY ON ROUTING PATHS

Adjustable Interface Buffer Circuit Between A Programmable Logic De...

FPGA Programming Structure for ATPG Test Coverage

Low Power Mode

Adjustable interface buffer circuit between a programmable logic de...

SERIALIZER/DESERIALIZER EMBEDDED IN A PROGRAMMABLE DEVICE