Ketan Padalia

Person

Thornhill, CA

People

Patents Grantslast 30 patents

Information Patent Grant
Method and apparatus for performing fast incremental physical desig...
- Patent number 11,093,672
- Issue date Aug 17, 2021
- Altera Corporation
- Junaid Asim Khan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing fast incremental physical desig...
- Patent number 10,635,772
- Issue date Apr 28, 2020
- Altera Corporation
- Junaid Asim Khan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing efficient incremental compilation
- Patent number 10,073,941
- Issue date Sep 11, 2018
- Altera Corporation
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structures for LUT-based arithmetic in PLDs
- Patent number 9,658,830
- Issue date May 23, 2017
- Altera Corporation
- Ketan Padalia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Apparatus and associated methods for parallelizing clustering and p...
- Patent number 9,594,859
- Issue date Mar 14, 2017
- Altera Corporation
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing fast incremental physical desig...
- Patent number 9,569,574
- Issue date Feb 14, 2017
- Altera Corporation
- Junaid Asim Khan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing efficient incremental compilation
- Patent number 8,856,713
- Issue date Oct 7, 2014
- Altera Corporation
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structures for LUT-based arithmetic in PLDs
- Patent number 8,788,550
- Issue date Jul 22, 2014
- Altera Corporation
- Ketan Padalia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and apparatus for performing efficient incremental compilation
- Patent number 8,539,418
- Issue date Sep 17, 2013
- Altera Corporation
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing automated timing closure analys...
- Patent number 8,504,970
- Issue date Aug 6, 2013
- Altera Corporation
- Shawn Malhotra
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for optimizing placement and routing
- Patent number 8,499,273
- Issue date Jul 30, 2013
- Altera Corporation
- Kimberley Anne Bozman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing efficient incremental compilation
- Patent number 8,281,274
- Issue date Oct 2, 2012
- Altera Corporation
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for grouping circuit elements into logic blocks
- Patent number 7,707,532
- Issue date Apr 27, 2010
- Altera Corporation
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for congestion estimation and optimization fo...
- Patent number 7,681,165
- Issue date Mar 16, 2010
- Altera Corporation
- Jason Peters
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Structures for LUT-based arithmetic in PLDs
- Patent number 7,558,812
- Issue date Jul 7, 2009
- Altera Corporation
- Ketan Padalia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods of packing user logical RAM into dedicated RAM blocks and d...
- Patent number 7,493,585
- Issue date Feb 17, 2009
- Altera Corporation
- Elias Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for designing integrated circuits
- Patent number 7,441,208
- Issue date Oct 21, 2008
- Altera Corporation
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic adjustment of optimization effort in configuring programm...
- Patent number 7,415,682
- Issue date Aug 19, 2008
- Altera Corporation
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for mapping logic design memory into physical memory devices...
- Patent number 7,370,291
- Issue date May 6, 2008
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques for grouping circuit elements into logic blocks
- Patent number 7,275,228
- Issue date Sep 25, 2007
- Altera Corporation
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adder circuitry for a programmable logic device
- Patent number 7,268,584
- Issue date Sep 11, 2007
- Altera Corporation
- David Cashman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for mapping logic design memory into physical memory device...
- Patent number 6,871,328
- Issue date Mar 22, 2005
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND APPARATUS FOR PERFORMING FAST INCREMENTAL PHYSICAL DESIG...
- Publication number 20200257839
- Publication date Aug 13, 2020
- Altera Corporation
- Junaid Asim Khan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURES FOR LUT-BASED ARITHMETIC IN PLDS
- Publication number 20170322775
- Publication date Nov 9, 2017
- Altera Corporation
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Methods for Parallelizing Integrated Circuit Computer...
- Publication number 20100070979
- Publication date Mar 18, 2010
- Adrian Ludwin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Methods for Congestion Estimation and Optimization fo...
- Publication number 20080059931
- Publication date Mar 6, 2008
- Jason Peters
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and methods for parallelizing integrated circuit computer...
- Publication number 20070192766
- Publication date Aug 16, 2007
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Automatic adjustment of optimization effort in configuring programm...
- Publication number 20060225021
- Publication date Oct 5, 2006
- Altera Corporation
- Ketan Padalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for mapping logic design memory into physical memory devices...
- Publication number 20050204325
- Publication date Sep 15, 2005
- Altera Corporation
- Ryan Fung
- G06 - COMPUTING CALCULATING COUNTING

Ketan Padalia

Person

Patents Grantslast 30 patents

Method and apparatus for performing fast incremental physical desig...

Method and apparatus for performing fast incremental physical desig...

Method and apparatus for performing efficient incremental compilation

Structures for LUT-based arithmetic in PLDs

Apparatus and associated methods for parallelizing clustering and p...

Method and apparatus for performing fast incremental physical desig...

Method and apparatus for performing efficient incremental compilation

Structures for LUT-based arithmetic in PLDs

Method and apparatus for performing efficient incremental compilation

Method and apparatus for performing automated timing closure analys...

Systems and methods for optimizing placement and routing

Method and apparatus for performing efficient incremental compilation

Techniques for grouping circuit elements into logic blocks

Apparatus and methods for congestion estimation and optimization fo...

Structures for LUT-based arithmetic in PLDs

Methods of packing user logical RAM into dedicated RAM blocks and d...

Methods for designing integrated circuits

Automatic adjustment of optimization effort in configuring programm...

Method for mapping logic design memory into physical memory devices...

Techniques for grouping circuit elements into logic blocks

Adder circuitry for a programmable logic device

Method for mapping logic design memory into physical memory device...

Patents Applicationslast 30 patents

METHOD AND APPARATUS FOR PERFORMING FAST INCREMENTAL PHYSICAL DESIG...

STRUCTURES FOR LUT-BASED ARITHMETIC IN PLDS

Apparatus and Methods for Parallelizing Integrated Circuit Computer...

Apparatus and Methods for Congestion Estimation and Optimization fo...

Apparatus and methods for parallelizing integrated circuit computer...

Automatic adjustment of optimization effort in configuring programm...

Method for mapping logic design memory into physical memory devices...