Kevin Lee Baker

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Efficient fabrication of memory structures
- Patent number 12,082,425
- Issue date Sep 3, 2024
- Micron Technology, Inc.
- Don Koun Lee
Information Patent Grant
Low resistance crosspoint architecture
- Patent number 11,882,774
- Issue date Jan 23, 2024
- Micron Technology, Inc.
- Rajasekhar Venigalla
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory with optimized resistive layers
- Patent number 11,778,837
- Issue date Oct 3, 2023
- Micron Technology, Inc.
- Lei Wei
Information Patent Grant
Methods for forming memory devices, and associated devices and systems
- Patent number 11,735,473
- Issue date Aug 22, 2023
- Micron Technology, Inc.
- Jukuan Zheng
- G11 - INFORMATION STORAGE
Information Patent Grant
Efficient fabrication of memory structures
- Patent number 11,626,452
- Issue date Apr 11, 2023
- Micron Technology, Inc.
- Don Koun Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory with optimized resistive layers
- Patent number 11,380,732
- Issue date Jul 5, 2022
- Micron Technology, Inc.
- Lei Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for forming memory devices, and associated devices and systems
- Patent number 11,201,083
- Issue date Dec 14, 2021
- Micron Technology, Inc.
- Jukuan Zheng
- G11 - INFORMATION STORAGE
Information Patent Grant
Low resistance crosspoint architecture
- Patent number 11,121,317
- Issue date Sep 14, 2021
- Micron Technology, Inc.
- Rajasekhar Venigalla
- G11 - INFORMATION STORAGE
Information Patent Grant
Dielectric barrier at non-volatile memory tile edge
- Patent number 11,069,855
- Issue date Jul 20, 2021
- Intel Corporation
- Kevin L. Baker
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-layer dielectric in memory device
- Patent number 10,629,652
- Issue date Apr 21, 2020
- Intel Corporation
- Michael J. Bernhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-layer dielectric in memory device
- Patent number 10,134,809
- Issue date Nov 20, 2018
- Intel Corporation
- Michael J. Bernhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-layer dielectric in memory device
- Patent number 9,704,923
- Issue date Jul 11, 2017
- Intel Corporation
- Michael J. Bernhardt
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
LOW RESISTANCE CROSSPOINT ARCHITECTURE
- Publication number 20240224825
- Publication date Jul 4, 2024
- Micron Technology, Inc.
- Rajasekhar Venigalla
- G11 - INFORMATION STORAGE
Information Patent Application
Integrated Circuitry, Array Of Cross-Point Memory Cells, Method Use...
- Publication number 20230371282
- Publication date Nov 16, 2023
- Micron Technology, Inc.
- David A. Kewley
- G11 - INFORMATION STORAGE
Information Patent Application
EFFICIENT FABRICATION OF MEMORY STRUCTURES
- Publication number 20230225137
- Publication date Jul 13, 2023
- Micron Technology, Inc.
- Don Koun Lee
Information Patent Application
MEMORY WITH OPTIMIZED RESISTIVE LAYERS
- Publication number 20220406847
- Publication date Dec 22, 2022
- Micron Technology, Inc.
- Lei Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW RESISTANCE CROSSPOINT ARCHITECTURE
- Publication number 20220069216
- Publication date Mar 3, 2022
- Micron Technology, Inc.
- Rajasekhar Venigalla
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS FOR FORMING MEMORY DEVICES, AND ASSOCIATED DEVICES AND SYSTEMS
- Publication number 20220068702
- Publication date Mar 3, 2022
- Micron Technology, Inc.
- Jukuan Zheng
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY WITH OPTIMIZED RESISTIVE LAYERS
- Publication number 20220037403
- Publication date Feb 3, 2022
- Micron Technology, Inc.
- Lei Wei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EFFICIENT FABRICATION OF MEMORY STRUCTURES
- Publication number 20220037402
- Publication date Feb 3, 2022
- Micron Technology, Inc.
- Don Koun Lee
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC BARRIER AT NON-VOLATILE MEMORY TILE EDGE
- Publication number 20210296582
- Publication date Sep 23, 2021
- Intel Corporation
- Kevin L. BAKER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS FOR FORMING MEMORY DEVICES, AND ASSOCIATED DEVICES AND SYSTEMS
- Publication number 20210202299
- Publication date Jul 1, 2021
- Micron Technology, Inc.
- Jukuan Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW RESISTANCE CROSSPOINT ARCHITECTURE
- Publication number 20210151675
- Publication date May 20, 2021
- Micron Technology, Inc.
- Rajasekhar Venigalla
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC BARRIER AT NON-VOLATILE MEMORY TILE EDGE
- Publication number 20210005810
- Publication date Jan 7, 2021
- Intel Corporation
- Kevin L. BAKER
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL-LAYER DIELECTRIC IN MEMORY DEVICE
- Publication number 20190206942
- Publication date Jul 4, 2019
- Intel Corporation
- Michael J. Bernhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DUAL-LAYER DIELECTRIC IN MEMORY DEVICE
- Publication number 20170271412
- Publication date Sep 21, 2017
- Intel Corporation
- Michael J. Bernhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual-layer dielectric in memory device
- Publication number 20170186815
- Publication date Jun 29, 2017
- Intel Corporation
- Michael J. Bernhardt
- H01 - BASIC ELECTRIC ELEMENTS

Kevin Lee Baker

Person

Patents Grantslast 30 patents

Efficient fabrication of memory structures

Low resistance crosspoint architecture

Memory with optimized resistive layers

Methods for forming memory devices, and associated devices and systems

Efficient fabrication of memory structures

Memory with optimized resistive layers

Methods for forming memory devices, and associated devices and systems

Low resistance crosspoint architecture

Dielectric barrier at non-volatile memory tile edge

Dual-layer dielectric in memory device

Dual-layer dielectric in memory device

Dual-layer dielectric in memory device

Patents Applicationslast 30 patents

LOW RESISTANCE CROSSPOINT ARCHITECTURE

Integrated Circuitry, Array Of Cross-Point Memory Cells, Method Use...

EFFICIENT FABRICATION OF MEMORY STRUCTURES

MEMORY WITH OPTIMIZED RESISTIVE LAYERS

LOW RESISTANCE CROSSPOINT ARCHITECTURE

METHODS FOR FORMING MEMORY DEVICES, AND ASSOCIATED DEVICES AND SYSTEMS

MEMORY WITH OPTIMIZED RESISTIVE LAYERS

EFFICIENT FABRICATION OF MEMORY STRUCTURES

DIELECTRIC BARRIER AT NON-VOLATILE MEMORY TILE EDGE

METHODS FOR FORMING MEMORY DEVICES, AND ASSOCIATED DEVICES AND SYSTEMS

LOW RESISTANCE CROSSPOINT ARCHITECTURE

DIELECTRIC BARRIER AT NON-VOLATILE MEMORY TILE EDGE

DUAL-LAYER DIELECTRIC IN MEMORY DEVICE

DUAL-LAYER DIELECTRIC IN MEMORY DEVICE

Dual-layer dielectric in memory device