Kevin W. Gorman

Person

Essex, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory bypass function for a memory
- Patent number 11,017,873
- Issue date May 25, 2021
- Synopsys, Inc.
- John Edward Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory bypass function for a memory
- Patent number 10,650,906
- Issue date May 12, 2020
- Synopsys, Inc.
- John Edward Barth
- G11 - INFORMATION STORAGE
Information Patent Grant
Arbitration for memory diagnostics
- Patent number 10,622,090
- Issue date Apr 14, 2020
- International Business Machines Corporation
- Aravindan J. Busi
- G01 - MEASURING TESTING
Information Patent Grant
Arbitration for memory diagnostics
- Patent number 10,153,055
- Issue date Dec 11, 2018
- International Business Machines Corporation
- Aravindan J. Busi
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory built-in self test system
- Patent number 9,946,620
- Issue date Apr 17, 2018
- Invecas, Inc.
- Kevin W. Gorman
- G11 - INFORMATION STORAGE
Information Patent Grant
Diagnostics for a memory device
- Patent number 9,865,361
- Issue date Jan 9, 2018
- Invecas, Inc.
- Thomas Chadwick
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-domain fuse management
- Patent number 9,799,413
- Issue date Oct 24, 2017
- Invecas, Inc.
- Kevin W. Gorman
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in-self-test (BIST) test time reduction
- Patent number 9,773,570
- Issue date Sep 26, 2017
- International Business Machines Corporation
- Kevin W. Gorman
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory test with in-line error correction code logic to test memory...
- Patent number 9,734,920
- Issue date Aug 15, 2017
- International Business Machines Corporation
- Kevin W. Gorman
- G11 - INFORMATION STORAGE
Information Patent Grant
Fast auto shift of failing memory diagnostics data using pattern de...
- Patent number 9,514,844
- Issue date Dec 6, 2016
- GLOBALFOUNDRIES Inc.
- Aravindan J. Busi
- G11 - INFORMATION STORAGE
Information Patent Grant
Read only memory (ROM) with redundancy
- Patent number 9,460,811
- Issue date Oct 4, 2016
- GLOBALFOUNDRIES Inc.
- George M. Braceras
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory test with in-line error correction code logic
- Patent number 9,224,503
- Issue date Dec 29, 2015
- International Business Machines Corporation
- Kevin W. Gorman
- G11 - INFORMATION STORAGE
Information Patent Grant
Verifying partial good voltage island structures
- Patent number 9,172,373
- Issue date Oct 27, 2015
- GlobalFoundries U.S. 2 LLC
- Kevin W. Gorman
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Staggered start of BIST controllers and BIST engines
- Patent number 8,935,586
- Issue date Jan 13, 2015
- International Business Machines Corporation
- Valarie H. Chickanosky
- G01 - MEASURING TESTING
Information Patent Grant
Bypass structure for a memory device and method to reduce unknown t...
- Patent number 8,917,566
- Issue date Dec 23, 2014
- International Business Machines Corporation
- Aaron J. Cummings
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method of reducing test time via address aware BIST circ...
- Patent number 8,914,688
- Issue date Dec 16, 2014
- International Business Machines Corporation
- George M. Belansek
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked chip module with integrated circuit chips having integratab...
- Patent number 8,872,322
- Issue date Oct 28, 2014
- International Business Machines Corporation
- Kevin W. Gorman
- G11 - INFORMATION STORAGE
Information Patent Grant
Stacked chip module with integrated circuit chips having integratab...
- Patent number 8,853,847
- Issue date Oct 7, 2014
- International Business Machines Corporation
- Kevin W. Gorman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Read only memory (ROM) with redundancy
- Patent number 8,839,054
- Issue date Sep 16, 2014
- International Business Machines Corporation
- George M. Braceras
- G11 - INFORMATION STORAGE
Information Patent Grant
Interleaving of memory repair data compression and fuse programming...
- Patent number 8,719,648
- Issue date May 6, 2014
- International Business Machines Corporation
- Kevin W. Gorman
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for efficient memory repair
- Patent number 8,612,813
- Issue date Dec 17, 2013
- International Business Machines Corporation
- Valerie H. Chickanosky
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and systems for adjusting wordline up-level voltage to impr...
- Patent number 8,582,351
- Issue date Nov 12, 2013
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Grant
Selectable repair pass masking
- Patent number 8,570,820
- Issue date Oct 29, 2013
- International Business Machines Corporation
- Kevin William Gorman
- G11 - INFORMATION STORAGE
Information Patent Grant
Fusebay controller structure, system, and method
- Patent number 8,484,543
- Issue date Jul 9, 2013
- International Business Machines Corporation
- Darren L. Anand
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure and method for storing multiple repair pass data into a f...
- Patent number 8,467,260
- Issue date Jun 18, 2013
- International Business Machines Corporation
- Kevin W. Gorman
- G11 - INFORMATION STORAGE
Information Patent Grant
Circuit and method for efficient memory repair
- Patent number 8,381,052
- Issue date Feb 19, 2013
- International Business Machines Corporation
- Valerie H. Chickanosky
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for a robust embedded interface
- Patent number 8,239,715
- Issue date Aug 7, 2012
- International Business Machines Corporation
- Steven M. Eustis
- G11 - INFORMATION STORAGE
Information Patent Grant
Structure for indicating status of an on-chip power supply system
- Patent number 8,028,195
- Issue date Sep 27, 2011
- International Business Machines Corporation
- Darren Anand
- G01 - MEASURING TESTING
Information Patent Grant
Structure for redundancy programming of a memory device
- Patent number 7,954,028
- Issue date May 31, 2011
- International Business Machines Corporation
- John Edward Barth, Jr.
- G11 - INFORMATION STORAGE
Information Patent Grant
Design structure and apparatus for a robust embedded interface
- Patent number 7,937,632
- Issue date May 3, 2011
- International Business Machines Corporation
- Steven M. Eustis
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
Memory Bypass Function For A Memory
- Publication number 20200234784
- Publication date Jul 23, 2020
- Synopsys, Inc.
- John Edward Barth
- G11 - INFORMATION STORAGE
Information Patent Application
Memory Bypass Function For A Memory
- Publication number 20200051658
- Publication date Feb 13, 2020
- Invecas, Inc.
- John Edward Barth
- G11 - INFORMATION STORAGE
Information Patent Application
ARBITRATION FOR MEMORY DIAGNOSTICS
- Publication number 20190035486
- Publication date Jan 31, 2019
- International Business Machines Corporation
- Aravindan J. BUSI
- G11 - INFORMATION STORAGE
Information Patent Application
Diagnostics for a Memory Device
- Publication number 20170316837
- Publication date Nov 2, 2017
- Invecas, Inc.
- Thomas Chadwick
- G11 - INFORMATION STORAGE
Information Patent Application
ARBITRATION FOR MEMORY DIAGNOSTICS
- Publication number 20160284426
- Publication date Sep 29, 2016
- International Business Machines Corporation
- Aravindan J. BUSI
- G11 - INFORMATION STORAGE
Information Patent Application
Multi-Domain Fuse Management
- Publication number 20160224451
- Publication date Aug 4, 2016
- Invecas, Inc.
- Kevin W. Gorman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory Built-In Self Test System
- Publication number 20160224450
- Publication date Aug 4, 2016
- Invecas, Inc.
- Kevin W. Gorman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAST AUTO SHIFT OF FAILING MEMORY DIAGNOSTICS DATA USING PATTERN DE...
- Publication number 20160064102
- Publication date Mar 3, 2016
- International Business Machines Corporation
- Aravindan J. BUSI
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY TEST WITH IN-LINE ERROR CORRECTION CODE LOGIC
- Publication number 20160019981
- Publication date Jan 21, 2016
- International Business Machines Corporation
- Kevin W. GORMAN
- G11 - INFORMATION STORAGE
Information Patent Application
VERIFYING PARTIAL GOOD VOLTAGE ISLAND STRUCTURES
- Publication number 20150070048
- Publication date Mar 12, 2015
- International Business Machines Corporation
- Kevin W. GORMAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ ONLY MEMORY (ROM) WITH REDUNDANCY
- Publication number 20140351662
- Publication date Nov 27, 2014
- George M. BRACERAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUILT-IN-SELF-TEST (BIST) TEST TIME REDUCTION
- Publication number 20140258797
- Publication date Sep 11, 2014
- International Business Machines Corporation
- Kevin W. Gorman
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEM AND METHOD OF REDUCING TEST TIME VIA ADDRESS AWARE BIST CIRC...
- Publication number 20140149810
- Publication date May 29, 2014
- International Business Machines Corporation
- George M. Belansek
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY TEST WITH IN-LINE ERROR CORRECTION CODE LOGIC
- Publication number 20140143619
- Publication date May 22, 2014
- International Business Machines Corporation
- Kevin W. GORMAN
- G11 - INFORMATION STORAGE
Information Patent Application
STAGGERED START OF BIST CONTROLLERS AND BIST ENGINES
- Publication number 20140129888
- Publication date May 8, 2014
- International Business Machines Corporation
- Valerie H. Chickanosky
- G01 - MEASURING TESTING
Information Patent Application
STACKED CHIP MODULE WITH INTEGRATED CIRCUIT CHIPS HAVING INTEGRATAB...
- Publication number 20140110711
- Publication date Apr 24, 2014
- International Business Machines Corporation
- Kevin W. Gorman
- G01 - MEASURING TESTING
Information Patent Application
STACKED CHIP MODULE WITH INTEGRATED CIRCUIT CHIPS HAVING INTEGRATAB...
- Publication number 20140110710
- Publication date Apr 24, 2014
- International Business Machines Corporation
- Kevin W. Gorman
- G01 - MEASURING TESTING
Information Patent Application
READ ONLY MEMORY (ROM) WITH REDUNDANCY
- Publication number 20130275821
- Publication date Oct 17, 2013
- International Business Machines Corporation
- George M. BRACERAS
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BYPASS STRUCTURE FOR A MEMORY DEVICE AND METHOD TO REDUCE UNKNOWN T...
- Publication number 20130272072
- Publication date Oct 17, 2013
- International Business Machines Corporation
- Aaron J. Cummings
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT AND METHOD FOR EFFICIENT MEMORY REPAIR
- Publication number 20130139010
- Publication date May 30, 2013
- International Business Machines Corporation
- Valerie H. CHICKANOSKY
- G11 - INFORMATION STORAGE
Information Patent Application
FUSEBAY CONTROLLER STRUCTURE, SYSTEM, AND METHOD
- Publication number 20130042166
- Publication date Feb 14, 2013
- International Business Machines Corporation
- Darren L. Anand
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STRUCTURE AND METHOD FOR STORING MULTIPLE REPAIR PASS DATA INTO A F...
- Publication number 20130033951
- Publication date Feb 7, 2013
- International Business Machines Corporation
- Kevin W. Gorman
- G11 - INFORMATION STORAGE
Information Patent Application
INTERLEAVING OF MEMORY REPAIR DATA COMPRESSION AND FUSE PROGRAMMING...
- Publication number 20130031319
- Publication date Jan 31, 2013
- International Business Machines Corporation
- Kevin W. Gorman
- G11 - INFORMATION STORAGE
Information Patent Application
SELECTABLE REPAIR PASS MASKING
- Publication number 20120230136
- Publication date Sep 13, 2012
- International Business Machines Corporation
- Kevin William Gorman
- G11 - INFORMATION STORAGE
Information Patent Application
Methods and Systems for Adjusting Wordline Up-Level Voltage to Impr...
- Publication number 20120075919
- Publication date Mar 29, 2012
- International Business Machines Corporation
- Igor Arsovski
- G11 - INFORMATION STORAGE
Information Patent Application
CIRCUIT AND METHOD FOR EFFICIENT MEMORY REPAIR
- Publication number 20110113280
- Publication date May 12, 2011
- International Business Machines Corporation
- Valerie H. CHICKANOSKY
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD, APPARATUS, AND DESIGN STRUCTURE FOR BUILT-IN SELF-TEST
- Publication number 20110029827
- Publication date Feb 3, 2011
- International Business Machines Corporation
- VALERIE H CHICKANOSKY
- G11 - INFORMATION STORAGE
Information Patent Application
STRUCTURE AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE
- Publication number 20090319841
- Publication date Dec 24, 2009
- Steven M. Eustis
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE
- Publication number 20090319818
- Publication date Dec 24, 2009
- Steven M. Eustis
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATION OF LBIST INTO ARRAY BISR FLOW
- Publication number 20090251978
- Publication date Oct 8, 2009
- International Business Machines Corporation
- Kevin W. Gorman
- H03 - BASIC ELECTRONIC CIRCUITRY

Kevin W. Gorman

Person

Patents Grantslast 30 patents

Memory bypass function for a memory

Memory bypass function for a memory

Arbitration for memory diagnostics

Arbitration for memory diagnostics

Memory built-in self test system

Diagnostics for a memory device

Multi-domain fuse management

Built-in-self-test (BIST) test time reduction

Memory test with in-line error correction code logic to test memory...

Fast auto shift of failing memory diagnostics data using pattern de...

Read only memory (ROM) with redundancy

Memory test with in-line error correction code logic

Verifying partial good voltage island structures

Staggered start of BIST controllers and BIST engines

Bypass structure for a memory device and method to reduce unknown t...

System and method of reducing test time via address aware BIST circ...

Stacked chip module with integrated circuit chips having integratab...

Stacked chip module with integrated circuit chips having integratab...

Read only memory (ROM) with redundancy

Interleaving of memory repair data compression and fuse programming...

Circuit and method for efficient memory repair

Methods and systems for adjusting wordline up-level voltage to impr...

Selectable repair pass masking

Fusebay controller structure, system, and method

Structure and method for storing multiple repair pass data into a f...

Circuit and method for efficient memory repair

Method and apparatus for a robust embedded interface

Structure for indicating status of an on-chip power supply system

Structure for redundancy programming of a memory device

Design structure and apparatus for a robust embedded interface

Patents Applicationslast 30 patents

Memory Bypass Function For A Memory

Memory Bypass Function For A Memory

ARBITRATION FOR MEMORY DIAGNOSTICS

Diagnostics for a Memory Device

ARBITRATION FOR MEMORY DIAGNOSTICS

Multi-Domain Fuse Management

Memory Built-In Self Test System

FAST AUTO SHIFT OF FAILING MEMORY DIAGNOSTICS DATA USING PATTERN DE...

MEMORY TEST WITH IN-LINE ERROR CORRECTION CODE LOGIC

VERIFYING PARTIAL GOOD VOLTAGE ISLAND STRUCTURES

READ ONLY MEMORY (ROM) WITH REDUNDANCY

BUILT-IN-SELF-TEST (BIST) TEST TIME REDUCTION

SYSTEM AND METHOD OF REDUCING TEST TIME VIA ADDRESS AWARE BIST CIRC...

MEMORY TEST WITH IN-LINE ERROR CORRECTION CODE LOGIC

STAGGERED START OF BIST CONTROLLERS AND BIST ENGINES

STACKED CHIP MODULE WITH INTEGRATED CIRCUIT CHIPS HAVING INTEGRATAB...

STACKED CHIP MODULE WITH INTEGRATED CIRCUIT CHIPS HAVING INTEGRATAB...

READ ONLY MEMORY (ROM) WITH REDUNDANCY

BYPASS STRUCTURE FOR A MEMORY DEVICE AND METHOD TO REDUCE UNKNOWN T...

CIRCUIT AND METHOD FOR EFFICIENT MEMORY REPAIR

FUSEBAY CONTROLLER STRUCTURE, SYSTEM, AND METHOD

STRUCTURE AND METHOD FOR STORING MULTIPLE REPAIR PASS DATA INTO A F...

INTERLEAVING OF MEMORY REPAIR DATA COMPRESSION AND FUSE PROGRAMMING...

SELECTABLE REPAIR PASS MASKING

Methods and Systems for Adjusting Wordline Up-Level Voltage to Impr...

CIRCUIT AND METHOD FOR EFFICIENT MEMORY REPAIR

METHOD, APPARATUS, AND DESIGN STRUCTURE FOR BUILT-IN SELF-TEST

STRUCTURE AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE

METHOD AND APPARATUS FOR A ROBUST EMBEDDED INTERFACE

INTEGRATION OF LBIST INTO ARRAY BISR FLOW