Khaled Hasnat

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and methods including source gates
- Patent number 12,148,474
- Issue date Nov 19, 2024
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
Reducing power consumption in nonvolatile memory due to standby lea...
- Patent number 11,500,446
- Issue date Nov 15, 2022
- Intel Corporation
- Richard Fastow
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods including source gates
- Patent number 11,211,126
- Issue date Dec 28, 2021
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory array with shorting structure on a dummy array thereof, and...
- Patent number 11,195,575
- Issue date Dec 7, 2021
- Intel Corporation
- Jaydip Bharatkumar Patel
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense flags in a memory device
- Patent number 11,029,861
- Issue date Jun 8, 2021
- Micron Technology, Inc.
- Shafqat Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory arrays with bonded and shared logic circuitry
- Patent number 10,923,450
- Issue date Feb 16, 2021
- Intel Corporation
- Richard Fastow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device with reduced capacitance
- Patent number 10,861,867
- Issue date Dec 8, 2020
- Intel Corporation
- Khaled Hasnat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Channel conductivity in memory structures
- Patent number 10,854,746
- Issue date Dec 1, 2020
- Intel Corporation
- Prashant Majhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device with vertical string drivers
- Patent number 10,804,280
- Issue date Oct 13, 2020
- Intel Corporation
- Khaled Hasnat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and methods including source gates
- Patent number 10,783,967
- Issue date Sep 22, 2020
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
Three-dimensional (3D) memory with shared control circuitry using w...
- Patent number 10,651,153
- Issue date May 12, 2020
- Intel Corporation
- Richard Fastow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Wordline bridge in a 3D memory array
- Patent number 10,515,973
- Issue date Dec 24, 2019
- Intel Corporation
- Deepak Thimmegowda
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense flags in a memory device
- Patent number 10,409,506
- Issue date Sep 10, 2019
- Micron Technology, Inc.
- Shafqat Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods including source gates
- Patent number 10,170,189
- Issue date Jan 1, 2019
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense operation flags in a memory device
- Patent number 10,126,967
- Issue date Nov 13, 2018
- Micron Technology, Inc.
- Shafqat Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods including source gates
- Patent number 9,779,816
- Issue date Oct 3, 2017
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
Sense operation flags in a memory device
- Patent number 9,519,582
- Issue date Dec 13, 2016
- Micron Technology, Inc.
- Shafqat Ahmed
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods including source gates
- Patent number 9,378,839
- Issue date Jun 28, 2016
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
3-D memory arrays
- Patent number 9,219,070
- Issue date Dec 22, 2015
- Micron Technology, Inc.
- Deepak Thimmegowda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Sense operation flags in a memory device
- Patent number 9,135,998
- Issue date Sep 15, 2015
- Micron Technology, Inc.
- Shafqat Ahmed
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus and methods including source gates
- Patent number 8,797,806
- Issue date Aug 5, 2014
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Grant
Direct alignment scheme between multiple lithography layers
- Patent number 7,547,597
- Issue date Jun 16, 2009
- Intel Corporation
- Derchang Kau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Direct alignment scheme between multiple lithography layers
- Patent number 7,087,943
- Issue date Aug 8, 2006
- Intel Corporation
- Derchang Kau
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHODS INCLUDING SOURCE GATES
- Publication number 20220189552
- Publication date Jun 16, 2022
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
TIER ARCHITECTURE FOR 3-DIMENSIONAL CROSS POINT MEMORY
- Publication number 20220190029
- Publication date Jun 16, 2022
- Intel Corporation
- Derchang Kau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY ARRAY WITH SHORTING STRUCTURE ON A DUMMY ARRAY THEREOF, AND...
- Publication number 20210407582
- Publication date Dec 30, 2021
- Intel Corporation
- Jaydip Bharatkumar Patel
- G11 - INFORMATION STORAGE
Information Patent Application
APPARATUS AND METHODS INCLUDING SOURCE GATES
- Publication number 20210174874
- Publication date Jun 10, 2021
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCING POWER CONSUMPTION IN NONVOLATILE MEMORY DUE TO STANDBY LEA...
- Publication number 20210096634
- Publication date Apr 1, 2021
- Intel Corporation
- Richard FASTOW
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY ARRAYS WITH BONDED AND SHARED LOGIC CIRCUITRY
- Publication number 20200395328
- Publication date Dec 17, 2020
- Intel Corporation
- Richard Fastow
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CHANNEL CONDUCTIVITY IN MEMORY STRUCTURES
- Publication number 20200152793
- Publication date May 14, 2020
- Intel Corporation
- Prashant Majhi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE WITH A SPLIT STAIRCASE
- Publication number 20200152650
- Publication date May 14, 2020
- Intel Corporation
- Deepak Thimmegowda
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE FLAGS IN A MEMORY DEVICE
- Publication number 20190369887
- Publication date Dec 5, 2019
- Micron Technology, Inc.
- Shafqat Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS INCLUDING SOURCE GATES
- Publication number 20190279715
- Publication date Sep 12, 2019
- Micron Technology, Inc.
- Akira Goda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY DEVICE WITH VERTICAL STRING DRIVERS
- Publication number 20190043873
- Publication date Feb 7, 2019
- Intel Corporation
- Khaled Hasnat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WORDLINE BRIDGE IN A 3D MEMORY ARRAY
- Publication number 20190043874
- Publication date Feb 7, 2019
- Intel Corporation
- Deepak Thimmegowda
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH REDUCED CAPACITANCE
- Publication number 20190043882
- Publication date Feb 7, 2019
- Khaled Hasnat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL (3D) MEMORY WITH SHARED CONTROL CIRCUITRY USING W...
- Publication number 20190043836
- Publication date Feb 7, 2019
- Intel Corporation
- Richard FASTOW
- G11 - INFORMATION STORAGE
Information Patent Application
THREE-DIMENSIONAL (3D) MEMORY WITH CONTROL CIRCUITRY AND ARRAY IN S...
- Publication number 20190043868
- Publication date Feb 7, 2019
- Intel Corporation
- Khaled HASNAT
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE FLAGS IN A MEMORY DEVICE
- Publication number 20180373451
- Publication date Dec 27, 2018
- Micron Technology, Inc.
- Shafqat Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS INCLUDING SOURCE GATES
- Publication number 20180122481
- Publication date May 3, 2018
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE OPERATION FLAGS IN A MEMORY DEVICE
- Publication number 20170075613
- Publication date Mar 16, 2017
- Micron Technology, Inc.
- Shafqat Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS INCLUDING SOURCE GATES
- Publication number 20160343438
- Publication date Nov 24, 2016
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE OPERATION FLAGS IN A MEMORY DEVICE
- Publication number 20150363313
- Publication date Dec 17, 2015
- Micron Technology, Inc.
- Shafqat Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WORD LINE AND BIT LINE PROCESSING FOR CROSS-POINT MEMORIES
- Publication number 20140370664
- Publication date Dec 18, 2014
- Kiran Pangal
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHODS INCLUDING SOURCE GATES
- Publication number 20140340963
- Publication date Nov 20, 2014
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
3-D Memory Arrays
- Publication number 20140217488
- Publication date Aug 7, 2014
- Micron Technology, Inc.
- Deepak Thimmegowda
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUS AND METHODS INCLUDING SOURCE GATES
- Publication number 20130044549
- Publication date Feb 21, 2013
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE OPERATION FLAGS IN A MEMORY DEVICE
- Publication number 20120117306
- Publication date May 10, 2012
- Micron Technology, Inc.
- Shafqat Ahmed
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Direct alignment scheme between multiple lithography layers
- Publication number 20060267224
- Publication date Nov 30, 2006
- Derchang Kau
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Direct alignment scheme between multiple lithography layers
- Publication number 20040224262
- Publication date Nov 11, 2004
- Intel Corporation
- Derchang Kau
- H01 - BASIC ELECTRIC ELEMENTS

Khaled Hasnat

Person

Patents Grantslast 30 patents

Apparatus and methods including source gates

Reducing power consumption in nonvolatile memory due to standby lea...

Apparatus and methods including source gates

Memory array with shorting structure on a dummy array thereof, and...

Sense flags in a memory device

Memory arrays with bonded and shared logic circuitry

Memory device with reduced capacitance

Channel conductivity in memory structures

Memory device with vertical string drivers

Apparatus and methods including source gates

Three-dimensional (3D) memory with shared control circuitry using w...

Wordline bridge in a 3D memory array

Sense flags in a memory device

Apparatus and methods including source gates

Sense operation flags in a memory device

Apparatus and methods including source gates

Sense operation flags in a memory device

Apparatus and methods including source gates

3-D memory arrays

Sense operation flags in a memory device

Apparatus and methods including source gates

Direct alignment scheme between multiple lithography layers

Direct alignment scheme between multiple lithography layers

Patents Applicationslast 30 patents

APPARATUS AND METHODS INCLUDING SOURCE GATES

TIER ARCHITECTURE FOR 3-DIMENSIONAL CROSS POINT MEMORY

MEMORY ARRAY WITH SHORTING STRUCTURE ON A DUMMY ARRAY THEREOF, AND...

APPARATUS AND METHODS INCLUDING SOURCE GATES

REDUCING POWER CONSUMPTION IN NONVOLATILE MEMORY DUE TO STANDBY LEA...

MEMORY ARRAYS WITH BONDED AND SHARED LOGIC CIRCUITRY

CHANNEL CONDUCTIVITY IN MEMORY STRUCTURES

MEMORY DEVICE WITH A SPLIT STAIRCASE

SENSE FLAGS IN A MEMORY DEVICE

APPARATUS AND METHODS INCLUDING SOURCE GATES

MEMORY DEVICE WITH VERTICAL STRING DRIVERS

WORDLINE BRIDGE IN A 3D MEMORY ARRAY

MEMORY DEVICE WITH REDUCED CAPACITANCE

THREE-DIMENSIONAL (3D) MEMORY WITH SHARED CONTROL CIRCUITRY USING W...

THREE-DIMENSIONAL (3D) MEMORY WITH CONTROL CIRCUITRY AND ARRAY IN S...

SENSE FLAGS IN A MEMORY DEVICE

APPARATUS AND METHODS INCLUDING SOURCE GATES

SENSE OPERATION FLAGS IN A MEMORY DEVICE

APPARATUS AND METHODS INCLUDING SOURCE GATES

SENSE OPERATION FLAGS IN A MEMORY DEVICE

WORD LINE AND BIT LINE PROCESSING FOR CROSS-POINT MEMORIES

APPARATUS AND METHODS INCLUDING SOURCE GATES

3-D Memory Arrays

APPARATUS AND METHODS INCLUDING SOURCE GATES

SENSE OPERATION FLAGS IN A MEMORY DEVICE

Direct alignment scheme between multiple lithography layers

Direct alignment scheme between multiple lithography layers