Khalid Radouane

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Montbonnon Saint Martin, FR

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Patents Grantslast 30 patents

Information Patent Grant
Process for preparing cleaned surfaces of strained silicon
- Patent number 8,461,055
- Issue date Jun 11, 2013
- Soitec
- Khalid Radouane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods for recycling substrates and fabricating laminated wafers
- Patent number 8,324,075
- Issue date Dec 4, 2012
- Soitec
- Cecile Aulnette
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Reduction of watermarks in HF treatments of semiconducting substrates
- Patent number 8,076,219
- Issue date Dec 13, 2011
- S.O.I. Tec Silicon on Insulator Technologies
- Khalid Radouane
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
REDUCTION OF WATERMARKS IN HF TREATMENTS OF SEMICONDUCTING SUBSTRATES
- Publication number 20100255659
- Publication date Oct 7, 2010
- Khalid Radouane
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR RECYCLING A SUBSTRATE, LAMINATED WATER FABRICATING METHO...
- Publication number 20100181653
- Publication date Jul 22, 2010
- S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, S.A.
- Cecile Aulnette
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
IMPROVED PROCESS FOR PREPARING CLEANED SURFACES OF STRAINED SILICON
- Publication number 20100140746
- Publication date Jun 10, 2010
- S.O.I.TEC SILICON ON INSULATOR TECHNOLOGIES, S.A.
- Khalid Radouane
- H01 - BASIC ELECTRIC ELEMENTS