Khandker N. Quader

Person

Sunnyvale, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Quasi-volatile system-level memory
- Patent number 12,105,650
- Issue date Oct 1, 2024
- SUNRISE MEMORY CORPORATION
- Robert D. Norman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High capacity memory circuit with low effective latency
- Patent number 12,073,082
- Issue date Aug 27, 2024
- SUNRISE MEMORY CORPORATION
- Youn Cheul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device with embedded high-bandwidth, high-capacity memory using waf...
- Patent number 12,068,286
- Issue date Aug 20, 2024
- SUNRISE MEMORY CORPORATION
- Khandker Nazrul Quader
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device including modular memory units and modular circuit un...
- Patent number 11,923,341
- Issue date Mar 5, 2024
- SUNRISE MEMORY CORPORATION
- Khandker Nazrul Quader
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
High capacity memory circuit with low effective latency
- Patent number 11,675,500
- Issue date Jun 13, 2023
- SUNRISE MEMORY CORPORATION
- Youn Cheul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device with embedded high-bandwidth, high-capacity memory using waf...
- Patent number 11,670,620
- Issue date Jun 6, 2023
- SUNRISE MEMORY CORPORATION
- Khandker Nazrul Quader
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quasi-volatile system-level memory
- Patent number 11,580,038
- Issue date Feb 14, 2023
- SUNRISE MEMORY CORPORATION
- Robert D. Norman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Nonvolatile semiconductor memory device having protection function...
- Patent number 8,111,551
- Issue date Feb 7, 2012
- Kabushiki Kaisha Toshiba
- Tomoharu Tanaka
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile semiconductor memory device having protection function...
- Patent number 7,952,925
- Issue date May 31, 2011
- Kabushiki Kaisha Toshiba
- Tomoharu Tanaka
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile semiconductor memory device having protection function...
- Patent number 7,787,296
- Issue date Aug 31, 2010
- Kabushiki Kaisha Toshiba
- Tomoharu Tanaka
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of reducing disturbs in non-volatile memory
- Patent number 7,468,915
- Issue date Dec 23, 2008
- SanDisk Corporation
- Daniel C. Guterman
- G11 - INFORMATION STORAGE
Information Patent Grant
Read and erase verify methods and circuits suitable for low voltage...
- Patent number 7,420,846
- Issue date Sep 2, 2008
- SanDisk Corporation
- Jian Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile semiconductor memory device, electronic card using the...
- Patent number 7,394,704
- Issue date Jul 1, 2008
- Kabushiki Kaisha Toshiba
- Tomoharu Tanaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Erase inhibit in non-volatile memories
- Patent number 7,379,346
- Issue date May 27, 2008
- SanDisk Corporation
- Khandker N. Quader
- G11 - INFORMATION STORAGE
Information Patent Grant
Nonvolatile semiconductor memory device having protection function...
- Patent number 7,376,010
- Issue date May 20, 2008
- Kabushiki Kaisha Toshiba
- Tomoharu Tanaka
- G11 - INFORMATION STORAGE
Information Patent Grant
Operating techniques for reducing effects of coupling between stora...
- Patent number 7,224,613
- Issue date May 29, 2007
- SanDisk Corporation
- Jian Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of reducing disturbs in non-volatile memory
- Patent number 7,145,804
- Issue date Dec 5, 2006
- SanDisk Corporation
- Daniel C. Guterman
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for programming and inhibiting multi-level, non-v...
- Patent number 7,095,654
- Issue date Aug 22, 2006
- SanDisk Corporation
- Khandker N. Quader
- G11 - INFORMATION STORAGE
Information Patent Grant
Operating techniques for reducing effects of coupling between stora...
- Patent number 7,061,798
- Issue date Jun 13, 2006
- SanDisk Corporation
- Jian Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for reducing effects of coupling between storage element...
- Patent number 7,046,548
- Issue date May 16, 2006
- SanDisk Corporation
- Raul-Adrian Cernea
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile semiconductor memory device, electronic card using the...
- Patent number 6,990,018
- Issue date Jan 24, 2006
- Kabushiki Kaisha Toshiba
- Tomoharu Tanaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of reducing disturbs in non-volatile memory
- Patent number 6,977,844
- Issue date Dec 20, 2005
- SanDisk Corporation
- Daniel C. Guterman
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for programming and inhibiting multi-level, non-v...
- Patent number 6,967,872
- Issue date Nov 22, 2005
- SanDisk Corporation
- Khandker N. Quader
- G11 - INFORMATION STORAGE
Information Patent Grant
Erase inhibit in non-volatile memories
- Patent number 6,958,936
- Issue date Oct 25, 2005
- SanDisk Corporation
- Khandker N. Quader
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and system for programming and inhibiting multi-level, non-v...
- Patent number 6,944,068
- Issue date Sep 13, 2005
- SanDisk Corporation
- Khandker N. Quader
- G11 - INFORMATION STORAGE
Information Patent Grant
Method of reducing disturbs in non-volatile memory
- Patent number 6,888,752
- Issue date May 3, 2005
- SanDisk Corporation
- John S. Mangan
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for reducing effects of coupling between storage element...
- Patent number 6,870,768
- Issue date Mar 22, 2005
- SanDisk Corporation
- Raul-Adrian Cernea
- G11 - INFORMATION STORAGE
Information Patent Grant
Read and erase verify methods and circuits suitable for low voltage...
- Patent number 6,839,281
- Issue date Jan 4, 2005
- Jian Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-state nonvolatile memory capable of reducing effects of coupl...
- Patent number 6,807,095
- Issue date Oct 19, 2004
- SanDisk Corporation
- Jian Chen
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques for reducing effects of coupling between storage element...
- Patent number 6,781,877
- Issue date Aug 24, 2004
- SanDisk Corporation
- Raul-Adrian Cernea
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
QUASI-VOLATILE SYSTEM-LEVEL MEMORY
- Publication number 20240411711
- Publication date Dec 12, 2024
- Sunrise Memory Corporation
- Robert D. Norman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE WITH EMBEDDED HIGH-BANDWIDTH, HIGH-CAPACITY MEMORY USING WAF...
- Publication number 20240363592
- Publication date Oct 31, 2024
- Sunrise Memory Corporation
- Khandker Nazrul Quader
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH CAPACITY MEMORY CIRCUIT WITH LOW EFFECTIVE LATENCY
- Publication number 20240345736
- Publication date Oct 17, 2024
- Sunrise Memory Corporation
- Youn Cheul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH CAPACITY MEMORY CIRCUIT WITH LOW EFFECTIVE LATENCY
- Publication number 20230259283
- Publication date Aug 17, 2023
- Sunrise Memory Corporation
- Youn Cheul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE WITH EMBEDDED HIGH-BANDWIDTH, HIGH-CAPACITY MEMORY USING WAF...
- Publication number 20230260969
- Publication date Aug 17, 2023
- Sunrise Memory Corporation
- Khandker Nazrul Quader
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUASI-VOLATILE SYSTEM-LEVEL MEMORY
- Publication number 20230131169
- Publication date Apr 27, 2023
- Sunrise Memory Corporation
- Robert D. Norman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICE INCLUDING MODULAR MEMORY UNITS AND MODULAR CIRCUIT UN...
- Publication number 20210398949
- Publication date Dec 23, 2021
- Sunrise Memory Corporation
- Khandker Nazrul Quader
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUASI-VOLATILE SYSTEM-LEVEL MEMORY
- Publication number 20210248094
- Publication date Aug 12, 2021
- SUNRISE MEMORY CORPORATION
- Robert D. Norman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIGH CAPACITY MEMORY CIRCUIT WITH LOW EFFECTIVE LATENCY
- Publication number 20210247910
- Publication date Aug 12, 2021
- SUNRISE MEMORY CORPORATION
- Youn Cheul Kim
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DEVICE WITH EMBEDDED HIGH-BANDWIDTH, HIGH-CAPACITY MEMORY USING WAF...
- Publication number 20200243486
- Publication date Jul 30, 2020
- SUNRISE MEMORY CORPORATION
- Khandker Nazrul Quader
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING PROTECTION FUNCTION...
- Publication number 20110205794
- Publication date Aug 25, 2011
- Tomoharu TANAKA
- G11 - INFORMATION STORAGE
Information Patent Application
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING PROTECTION FUNCTION...
- Publication number 20100296339
- Publication date Nov 25, 2010
- Tomoharu TANAKA
- G11 - INFORMATION STORAGE
Information Patent Application
NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING PROTECTION FUNCTION...
- Publication number 20080205143
- Publication date Aug 28, 2008
- Tomoharu TANAKA
- G11 - INFORMATION STORAGE
Information Patent Application
Method of Reducing Disturbs in Non-Volatile Memory
- Publication number 20070076510
- Publication date Apr 5, 2007
- John S. Mangan
- G11 - INFORMATION STORAGE
Information Patent Application
Read and erase verify methods and circuits suitable for low voltage...
- Publication number 20070058435
- Publication date Mar 15, 2007
- SanDisk Corporation
- Jian Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Nonvolatile semiconductor memory device which uses some memory bloc...
- Publication number 20060171210
- Publication date Aug 3, 2006
- Hiroyuki Nagashima
- G11 - INFORMATION STORAGE
Information Patent Application
Nonvolatile semiconductor memory device having protection function...
- Publication number 20060164886
- Publication date Jul 27, 2006
- Tomoharu Tanaka
- G11 - INFORMATION STORAGE
Information Patent Application
Non-volatile semiconductor memory device, electronic card using the...
- Publication number 20060077712
- Publication date Apr 13, 2006
- Tomoharu Tanaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Erase inhibit in non-volatile memories
- Publication number 20060028876
- Publication date Feb 9, 2006
- Khandker N. Quader
- G11 - INFORMATION STORAGE
Information Patent Application
Method of reducing disturbs in non-volatile memory
- Publication number 20060023507
- Publication date Feb 2, 2006
- SanDisk Corporation
- John S. Mangan
- G11 - INFORMATION STORAGE
Information Patent Application
Method and system for programming and inhibiting multi-level, non-v...
- Publication number 20060007736
- Publication date Jan 12, 2006
- Khandker N. Quader
- G11 - INFORMATION STORAGE
Information Patent Application
Operating techniques for reducing effects of coupling between stora...
- Publication number 20050276101
- Publication date Dec 15, 2005
- Jian Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Method of reducing disturbs in non-volatile memory
- Publication number 20050146933
- Publication date Jul 7, 2005
- Daniel C. Guterman
- G11 - INFORMATION STORAGE
Information Patent Application
Techniques for reducing effects of coupling between storage element...
- Publication number 20050146931
- Publication date Jul 7, 2005
- Raul-Adrian Cernea
- G11 - INFORMATION STORAGE
Information Patent Application
ERASE INHIBIT IN NON-VOLATILE MEMORIES
- Publication number 20050068808
- Publication date Mar 31, 2005
- Khandker N. Quader
- G11 - INFORMATION STORAGE
Information Patent Application
Operating techniques for reducing effects of coupling between stora...
- Publication number 20050047223
- Publication date Mar 3, 2005
- Jian Chen
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES FOR REDUCING EFFECTS OF COUPLING BETWEEN STORAGE ELEMENT...
- Publication number 20050018482
- Publication date Jan 27, 2005
- Raul-Adrian Cemea
- G11 - INFORMATION STORAGE
Information Patent Application
Non-volatile semiconductor memory device, electronic card using the...
- Publication number 20040257874
- Publication date Dec 23, 2004
- Tomoharu Tanaka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ AND ERASE VERIFY METHODS AND CIRCUITS SUITABLE FOR LOW VOLTAGE...
- Publication number 20040202023
- Publication date Oct 14, 2004
- Jian Chen
- G11 - INFORMATION STORAGE
Information Patent Application
Method and system for programming and inhibiting multi-level, non-v...
- Publication number 20040179404
- Publication date Sep 16, 2004
- Khandker N. Quader
- G11 - INFORMATION STORAGE

Khandker N. Quader

Person

Patents Grantslast 30 patents

Quasi-volatile system-level memory

High capacity memory circuit with low effective latency

Device with embedded high-bandwidth, high-capacity memory using waf...

Memory device including modular memory units and modular circuit un...

High capacity memory circuit with low effective latency

Device with embedded high-bandwidth, high-capacity memory using waf...

Quasi-volatile system-level memory

Nonvolatile semiconductor memory device having protection function...

Nonvolatile semiconductor memory device having protection function...

Nonvolatile semiconductor memory device having protection function...

Method of reducing disturbs in non-volatile memory

Read and erase verify methods and circuits suitable for low voltage...

Non-volatile semiconductor memory device, electronic card using the...

Erase inhibit in non-volatile memories

Nonvolatile semiconductor memory device having protection function...

Operating techniques for reducing effects of coupling between stora...

Method of reducing disturbs in non-volatile memory

Method and system for programming and inhibiting multi-level, non-v...

Operating techniques for reducing effects of coupling between stora...

Techniques for reducing effects of coupling between storage element...

Non-volatile semiconductor memory device, electronic card using the...

Method of reducing disturbs in non-volatile memory

Method and system for programming and inhibiting multi-level, non-v...

Erase inhibit in non-volatile memories

Method and system for programming and inhibiting multi-level, non-v...

Method of reducing disturbs in non-volatile memory

Techniques for reducing effects of coupling between storage element...

Read and erase verify methods and circuits suitable for low voltage...

Multi-state nonvolatile memory capable of reducing effects of coupl...

Techniques for reducing effects of coupling between storage element...

Patents Applicationslast 30 patents

QUASI-VOLATILE SYSTEM-LEVEL MEMORY

DEVICE WITH EMBEDDED HIGH-BANDWIDTH, HIGH-CAPACITY MEMORY USING WAF...

HIGH CAPACITY MEMORY CIRCUIT WITH LOW EFFECTIVE LATENCY

HIGH CAPACITY MEMORY CIRCUIT WITH LOW EFFECTIVE LATENCY

DEVICE WITH EMBEDDED HIGH-BANDWIDTH, HIGH-CAPACITY MEMORY USING WAF...

QUASI-VOLATILE SYSTEM-LEVEL MEMORY

MEMORY DEVICE INCLUDING MODULAR MEMORY UNITS AND MODULAR CIRCUIT UN...

QUASI-VOLATILE SYSTEM-LEVEL MEMORY

HIGH CAPACITY MEMORY CIRCUIT WITH LOW EFFECTIVE LATENCY

DEVICE WITH EMBEDDED HIGH-BANDWIDTH, HIGH-CAPACITY MEMORY USING WAF...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING PROTECTION FUNCTION...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING PROTECTION FUNCTION...

NONVOLATILE SEMICONDUCTOR MEMORY DEVICE HAVING PROTECTION FUNCTION...

Method of Reducing Disturbs in Non-Volatile Memory

Read and erase verify methods and circuits suitable for low voltage...

Nonvolatile semiconductor memory device which uses some memory bloc...

Nonvolatile semiconductor memory device having protection function...

Non-volatile semiconductor memory device, electronic card using the...

Erase inhibit in non-volatile memories

Method of reducing disturbs in non-volatile memory

Method and system for programming and inhibiting multi-level, non-v...

Operating techniques for reducing effects of coupling between stora...

Method of reducing disturbs in non-volatile memory

Techniques for reducing effects of coupling between storage element...

ERASE INHIBIT IN NON-VOLATILE MEMORIES

Operating techniques for reducing effects of coupling between stora...

TECHNIQUES FOR REDUCING EFFECTS OF COUPLING BETWEEN STORAGE ELEMENT...

Non-volatile semiconductor memory device, electronic card using the...

READ AND ERASE VERIFY METHODS AND CIRCUITS SUITABLE FOR LOW VOLTAGE...

Method and system for programming and inhibiting multi-level, non-v...