Kimimasa Imai

Person

Kawasaki-shi, JP

People

Patents Grantslast 30 patents

Information Patent Grant
Semiconductor memory device and defective cell relieving method
- Patent number 8,837,240
- Issue date Sep 16, 2014
- Kabushiki Kaisha Toshiba
- Takayuki Iwai
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device and defective cell relieving method
- Patent number 8,675,431
- Issue date Mar 18, 2014
- Kabushiki Kaisha Toshiba
- Takayuki Iwai
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device having replica circuit
- Patent number 7,646,657
- Issue date Jan 12, 2010
- Kabushiki Kaisha Toshiba
- Kimimasa Imai
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device having layered bit line structure
- Patent number 7,433,259
- Issue date Oct 7, 2008
- Kabushiki Kaisha Toshiba
- Kimimasa Imai
- G11 - INFORMATION STORAGE
Information Patent Grant
Read/program potential generating circuit
- Patent number 6,920,070
- Issue date Jul 19, 2005
- Kabushiki Kaisha Toshiba
- Kimimasa Imai
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor device
- Patent number 6,081,468
- Issue date Jun 27, 2000
- Kabushiki Kaisha Toshiba
- Takashi Taira
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory incorporating a plurality of data input buffer...
- Patent number 5,424,984
- Issue date Jun 13, 1995
- Kabushiki Kaisha Toshiba
- Yousei Nagahama
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor memory device
- Patent number 5,404,336
- Issue date Apr 4, 1995
- Kabushiki Kaisha Toshiba
- Kimimasa Imai
- G11 - INFORMATION STORAGE
Information Patent Grant
Semiconductor circuit device for preventing an output of a bistable...
- Patent number 4,849,653
- Issue date Jul 18, 1989
- Kabushiki Kaisha Toshiba
- Kimimasa Imai
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR MEMORY DEVICE AND DEFECTIVE CELL RELIEVING METHOD
- Publication number 20130077420
- Publication date Mar 28, 2013
- Kabushiki Kaisha Toshiba
- Takayuki Iwai
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE AND DEFECTIVE CELL RELIEVING METHOD
- Publication number 20130051167
- Publication date Feb 28, 2013
- Kabushiki Kaisha Toshiba
- Takayuki Iwai
- G11 - INFORMATION STORAGE
Information Patent Application
SEMICONDUCTOR MEMORY DEVICE HAVING REPLICA CIRCUIT
- Publication number 20080123387
- Publication date May 29, 2008
- Kabushiki Kaisha Toshiba
- Kimimasa IMAI
- G11 - INFORMATION STORAGE
Information Patent Application
Semiconductor memory device having layered bit line structure
- Publication number 20070047368
- Publication date Mar 1, 2007
- Kimimasa Imai
- G11 - INFORMATION STORAGE
Information Patent Application
Read/program potential generating circuit
- Publication number 20050013188
- Publication date Jan 20, 2005
- Kimimasa Imai
- G11 - INFORMATION STORAGE

Kimimasa Imai

Person

Patents Grantslast 30 patents

Semiconductor memory device and defective cell relieving method

Semiconductor memory device and defective cell relieving method

Semiconductor memory device having replica circuit

Semiconductor memory device having layered bit line structure

Read/program potential generating circuit

Semiconductor device

Semiconductor memory incorporating a plurality of data input buffer...

Semiconductor memory device

Semiconductor circuit device for preventing an output of a bistable...

Patents Applicationslast 30 patents

SEMICONDUCTOR MEMORY DEVICE AND DEFECTIVE CELL RELIEVING METHOD

SEMICONDUCTOR MEMORY DEVICE AND DEFECTIVE CELL RELIEVING METHOD

SEMICONDUCTOR MEMORY DEVICE HAVING REPLICA CIRCUIT

Semiconductor memory device having layered bit line structure

Read/program potential generating circuit