Kin Hooi Dia

Person

Hsinchu City, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Logic cell with small cell delay
- Patent number 12,191,310
- Issue date Jan 7, 2025
- Mediatek Inc.
- Kin-Hooi Dia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Clock gating cells
- Patent number 12,081,214
- Issue date Sep 3, 2024
- Mediatek Inc.
- Kin-Hooi Dia
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Multi-bit flip-flop with power saving feature
- Patent number 11,714,125
- Issue date Aug 1, 2023
- Mediatek Inc.
- Kin-Hooi Dia
- G01 - MEASURING TESTING
Information Patent Grant
Standard cell circuitries
- Patent number 10,361,190
- Issue date Jul 23, 2019
- Mediatek Inc.
- Kin-Hooi Dia
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Scan test circuit with pulse generator for generating differential...
- Patent number 9,372,233
- Issue date Jun 21, 2016
- MediaTek Singapore Pte Ltd.
- Kin Hooi Dia
- G01 - MEASURING TESTING
Information Patent Grant
Pulse latches
- Patent number 8,970,274
- Issue date Mar 3, 2015
- MediaTek Singapore Pte Ltd.
- Joseph Patrick Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Scan test circuit with scan clock
- Patent number 8,904,252
- Issue date Dec 2, 2014
- MediaTek Singapore Pte. Ltd.
- Dimitry Patent
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
STANDARD CELL TOPOLOGY WITH POWER/PERFORMANCE/AREA OPTIMIZATION
- Publication number 20250005256
- Publication date Jan 2, 2025
- MEDIATEK INC.
- Ho-Chieh Hsieh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SEMICONDUCTOR STRUCTURE OF HYBRID CELL ARRAY
- Publication number 20230178537
- Publication date Jun 8, 2023
- MEDIATEK INC.
- Kin-Hooi DIA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor devices and multi-bit flip-flop circuits having an as...
- Publication number 20230179187
- Publication date Jun 8, 2023
- MEDIATEK INC.
- Yi-Horng Chiou
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SEMICONDUCTOR STRUCTURE OF LOGIC CELL WITH SMALL CELL DELAY
- Publication number 20230178557
- Publication date Jun 8, 2023
- MEDIATEK INC.
- Ho-Chieh HSIEH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE OF CELL ARRAY WITH ADAPTIVE THRESHOLD VOLTAGE
- Publication number 20220343053
- Publication date Oct 27, 2022
- MEDIATEK INC.
- Kin-Hooi DIA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC CELL WITH SMALL CELL DELAY
- Publication number 20220223623
- Publication date Jul 14, 2022
- MEDIATEK INC.
- Kin-Hooi DIA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MULTI-BIT FLIP-FLOP WITH POWER SAVING FEATURE
- Publication number 20210359667
- Publication date Nov 18, 2021
- MEDIATEK INC.
- Kin-Hooi Dia
- G01 - MEASURING TESTING
Information Patent Application
STANDARD CELL CIRCUITRIES
- Publication number 20170018572
- Publication date Jan 19, 2017
- MEDIATEK INC.
- Kin-Hooi DIA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SCAN TEST CIRCUIT WITH SCAN CLOCK
- Publication number 20150058690
- Publication date Feb 26, 2015
- MEDIATEK SINGAPORE PTE LTD
- Kin Hooi Dia
- G01 - MEASURING TESTING
Information Patent Application
PULSE LATCHES
- Publication number 20130328601
- Publication date Dec 12, 2013
- Joseph Patrick Geisler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
SCAN TEST CIRCUIT WITH SCAN CLOCK
- Publication number 20130031434
- Publication date Jan 31, 2013
- Dimitry Patent
- G01 - MEASURING TESTING

Kin Hooi Dia

Person

Patents Grantslast 30 patents

Logic cell with small cell delay

Clock gating cells

Multi-bit flip-flop with power saving feature

Standard cell circuitries

Scan test circuit with pulse generator for generating differential...

Pulse latches

Scan test circuit with scan clock

Patents Applicationslast 30 patents

STANDARD CELL TOPOLOGY WITH POWER/PERFORMANCE/AREA OPTIMIZATION

SEMICONDUCTOR STRUCTURE OF HYBRID CELL ARRAY

Semiconductor devices and multi-bit flip-flop circuits having an as...

SEMICONDUCTOR STRUCTURE OF LOGIC CELL WITH SMALL CELL DELAY

SEMICONDUCTOR STRUCTURE OF CELL ARRAY WITH ADAPTIVE THRESHOLD VOLTAGE

LOGIC CELL WITH SMALL CELL DELAY

MULTI-BIT FLIP-FLOP WITH POWER SAVING FEATURE

STANDARD CELL CIRCUITRIES

SCAN TEST CIRCUIT WITH SCAN CLOCK

PULSE LATCHES

SCAN TEST CIRCUIT WITH SCAN CLOCK