Kin Wai TANG

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Patents Grantslast 30 patents

Information Patent Grant
Integrated circuits and methods of forming integrated circuits
- Patent number 11,164,858
- Issue date Nov 2, 2021
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Benfu Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Etch bias control
- Patent number 9,520,299
- Issue date Dec 13, 2016
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Wanbing Yi
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method for reducing sidewall etch residue
- Patent number 8,153,527
- Issue date Apr 10, 2012
- GLOBALFOUNDRIES Singapore Pte. Ltd.
- Soon Yoong Loh
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Accurate processing through procedure validation in software contro...
- Patent number 6,466,945
- Issue date Oct 15, 2002
- Chartered Semiconductor Manufacturing Ltd.
- Carol Gual Choo Goh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for forming a transistor within an integrated circuit
- Patent number 6,303,451
- Issue date Oct 16, 2001
- Chartered Semiconductor Manufacturing, Ltd.
- Xin Zhang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUITS AND METHODS OF FORMING INTEGRATED CIRCUITS
- Publication number 20210288042
- Publication date Sep 16, 2021
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Benfu LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ETCH BIAS CONTROL
- Publication number 20160189971
- Publication date Jun 30, 2016
- GLOBALFOUNDRIES SINGAPORE PTE. LTD.
- Wanbing Yi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR REDUCING SIDEWALL ETCH RESIDUE
- Publication number 20100091424
- Publication date Apr 15, 2010
- CHARTERED SEMICONDUCTOR MANUFACTURING, LTD.
- Soon Yoong LOH
- H01 - BASIC ELECTRIC ELEMENTS