Kiran PANGAL

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Modified write voltage for memory devices
- Patent number 11,705,197
- Issue date Jul 18, 2023
- Micron Technology, Inc.
- Sandeepan Dasgupta
- G11 - INFORMATION STORAGE
Information Patent Grant
Current delivery and spike mitigation in a memory cell array
- Patent number 11,322,546
- Issue date May 3, 2022
- Intel Corporation
- Shafqat Ahmed
- G11 - INFORMATION STORAGE
Information Patent Grant
Modified write voltage for memory devices
- Patent number 11,170,853
- Issue date Nov 9, 2021
- Micron Technology, Inc.
- Sandeepan Dasgupta
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques to mitigate error during a read operation to a memory array
- Patent number 11,145,366
- Issue date Oct 12, 2021
- Intel Corporation
- Davide Mantegazza
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-level cell (MLC) cross-point memory
- Patent number 11,107,523
- Issue date Aug 31, 2021
- Intel Corporation
- Sanjay Rangan
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual demarcation voltage sensing before writes
- Patent number 11,024,380
- Issue date Jun 1, 2021
- Intel Corporation
- Daniel Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Multi-level cell (MLC) techniques and circuits for cross-point memory
- Patent number 10,957,387
- Issue date Mar 23, 2021
- Intel Corporation
- Davide Mantegazza
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced uncorrectable memory errors
- Patent number 10,936,418
- Issue date Mar 2, 2021
- Intel Corporation
- Kiran Pangal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transient current-protected threshold switching devices systems and...
- Patent number 10,902,911
- Issue date Jan 26, 2021
- Intel Corporation
- Davide Mantegazza
- G11 - INFORMATION STORAGE
Information Patent Grant
Multistage set procedure for phase change memory
- Patent number 10,783,966
- Issue date Sep 22, 2020
- Intel Corporation
- Sanjay Rangan
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross point memory control
- Patent number 10,546,634
- Issue date Jan 28, 2020
- Intel Corporation
- Raymond W. Zeng
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross-point memory single-selection write technique
- Patent number 10,497,434
- Issue date Dec 3, 2019
- Intel Corporation
- Mase J Taub
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual demarcation voltage sensing before writes
- Patent number 10,482,960
- Issue date Nov 19, 2019
- Intel Corporation
- Daniel Chu
- G11 - INFORMATION STORAGE
Information Patent Grant
Transient current-protected threshold switching devices systems and...
- Patent number 10,475,508
- Issue date Nov 12, 2019
- Intel Corporation
- Davide Mantegazza
- G11 - INFORMATION STORAGE
Information Patent Grant
Multistage set procedure for phase change memory
- Patent number 10,446,229
- Issue date Oct 15, 2019
- Intel Corporation
- Sanjay Rangan
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for multi-level setback read for three dimensi...
- Patent number 10,438,659
- Issue date Oct 8, 2019
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatuses for modulating threshold voltages of memory cells
- Patent number 10,431,270
- Issue date Oct 1, 2019
- Micron Technology, Inc.
- Davide Mantegazza
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for reducing silent data errors in non-volatil...
- Patent number 10,331,345
- Issue date Jun 25, 2019
- Intel Corporation
- Wei Fang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced uncorrectable memory errors
- Patent number 10,324,793
- Issue date Jun 18, 2019
- Intel Corporation
- Kiran Pangal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Techniques to mitigate bias drift for a memory device
- Patent number 10,269,396
- Issue date Apr 23, 2019
- Intel Corporation
- Rakesh Jeyasingh
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing disturbance induced errors
- Patent number 10,153,015
- Issue date Dec 11, 2018
- Intel Corporation
- Prashant S. Damle
- G11 - INFORMATION STORAGE
Information Patent Grant
Cross point memory control
- Patent number 10,134,468
- Issue date Nov 20, 2018
- Intel Corporation
- Raymond W. Zeng
- G11 - INFORMATION STORAGE
Information Patent Grant
Error correction in memory
- Patent number 10,073,731
- Issue date Sep 11, 2018
- Intel Corporation
- Ravi H. Motwani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cross-point memory single-selection write technique
- Patent number 10,056,136
- Issue date Aug 21, 2018
- Intel Corporation
- Mase J Taub
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus for multi-level setback read for three dimensi...
- Patent number 10,032,508
- Issue date Jul 24, 2018
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Grant
Techniques to mitigate bias drift for a memory device
- Patent number 10,026,460
- Issue date Jul 17, 2018
- Intel Corporation
- Rakesh Jeyasingh
- G11 - INFORMATION STORAGE
Information Patent Grant
Reduced uncorrectable memory errors
- Patent number 9,934,088
- Issue date Apr 3, 2018
- Intel Corporation
- Kiran Pangal
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Methods and apparatuses for modulating threshold voltages of memory...
- Patent number 9,905,280
- Issue date Feb 27, 2018
- Micron Technology, Inc.
- Davide Mantegazza
- G11 - INFORMATION STORAGE
Information Patent Grant
Multistage set procedure for phase change memory
- Patent number 9,892,785
- Issue date Feb 13, 2018
- Intel Corporation
- Sanjay Rangan
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic window to improve NAND endurance
- Patent number 9,857,992
- Issue date Jan 2, 2018
- Intel Corporation
- Kiran Pangal
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
ENCODING ADDITIONAL STATES IN A THREE-DIMENSIONAL CROSSPOINT MEMORY...
- Publication number 20230064007
- Publication date Mar 2, 2023
- Intel Corporation
- Rouhollah Mousavi Iraei
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CROSS-POINT MEMORY READ TECHNIQUE TO MITIGATE DRIFT ERRORS
- Publication number 20220415425
- Publication date Dec 29, 2022
- Intel Corporation
- Hemant P. RAO
- G11 - INFORMATION STORAGE
Information Patent Application
MODIFIED WRITE VOLTAGE FOR MEMORY DEVICES
- Publication number 20220068385
- Publication date Mar 3, 2022
- Micron Technology, Inc.
- Sandeepan Dasgupta
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES TO MITIGATE ERROR DURING A READ OPERATION TO A MEMORY ARRAY
- Publication number 20210304817
- Publication date Sep 30, 2021
- Intel Corporation
- Davide MANTEGAZZA
- G11 - INFORMATION STORAGE
Information Patent Application
MODIFIED WRITE VOLTAGE FOR MEMORY DEVICES
- Publication number 20210280244
- Publication date Sep 9, 2021
- Micron Technology, Inc.
- Sandeepan Dasgupta
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL DEMARCATION VOLTAGE SENSING BEFORE WRITES
- Publication number 20200160908
- Publication date May 21, 2020
- Intel Corporation
- Daniel Chu
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSIENT CURRENT-PROTECTED THRESHOLD SWITCHING DEVICES SYSTEMS AND...
- Publication number 20200143881
- Publication date May 7, 2020
- Intel Corporation
- Davide Mantegazza
- G11 - INFORMATION STORAGE
Information Patent Application
MULTISTAGE SET PROCEDURE FOR PHASE CHANGE MEMORY
- Publication number 20200035300
- Publication date Jan 30, 2020
- Sanjay RANGAN
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCED UNCORRECTABLE MEMORY ERRORS
- Publication number 20190370112
- Publication date Dec 5, 2019
- Intel Corporation
- Kiran PANGAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR REDUCING SILENT DATA ERRORS IN NON-VOLATIL...
- Publication number 20190102088
- Publication date Apr 4, 2019
- Intel Corporation
- Wei Fang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CROSS POINT MEMORY CONTROL
- Publication number 20190096482
- Publication date Mar 28, 2019
- Intel Corporation
- Raymond W. Zeng
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS-POINT MEMORY SINGLE-SELECTION WRITE TECHNIQUE
- Publication number 20190074058
- Publication date Mar 7, 2019
- Intel Corporation
- Mase J Taub
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES TO MITIGATE BIAS DRIFT FOR A MEMORY DEVICE
- Publication number 20190057728
- Publication date Feb 21, 2019
- Intel Corporation
- Rakesh Jeyasingh
- G11 - INFORMATION STORAGE
Information Patent Application
CURRENT DELIVERY AND SPIKE MITIGATION IN A MEMORY CELL ARRAY
- Publication number 20190043923
- Publication date Feb 7, 2019
- Intel Corporation
- Shafqat AHMED
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND APPARATUS FOR MULTI-LEVEL SETBACK READ FOR THREE DIMENSI...
- Publication number 20190013071
- Publication date Jan 10, 2019
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSIENT CURRENT-PROTECTED THRESHOLD SWITCHING DEVICES SYSTEMS AND...
- Publication number 20180286478
- Publication date Oct 4, 2018
- Intel Corporation
- Davide Mantegazza
- G11 - INFORMATION STORAGE
Information Patent Application
REDUCED UNCORRECTABLE MEMORY ERRORS
- Publication number 20180253355
- Publication date Sep 6, 2018
- Intel Corporation
- Kiran PANGAL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC WINDOW TO IMPROVE NAND ENDURANCE
- Publication number 20180196612
- Publication date Jul 12, 2018
- Intel Corporation
- Kiran Pangal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR MULTI-LEVEL SETBACK READ FOR THREE DIMENSI...
- Publication number 20180190353
- Publication date Jul 5, 2018
- Intel Corporation
- Balaji Srinivasan
- G11 - INFORMATION STORAGE
Information Patent Application
MULTISTAGE SET PROCEDURE FOR PHASE CHANGE MEMORY
- Publication number 20180182456
- Publication date Jun 28, 2018
- Intel Corporation
- Sanjay RANGAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
APPARATUSES FOR MODULATING THRESHOLD VOLTAGES OF MEMORY CELLS
- Publication number 20180151206
- Publication date May 31, 2018
- Micron Technology, Inc.
- Davide Mantegazza
- G11 - INFORMATION STORAGE
Information Patent Application
MANAGING DISTURBANCE INDUCED ERRORS
- Publication number 20180068695
- Publication date Mar 8, 2018
- Intel Corporation
- Prashant S. DAMLE
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS-POINT MEMORY SINGLE-SELECTION WRITE TECHNIQUE
- Publication number 20170294228
- Publication date Oct 12, 2017
- Intel Corporation
- Mase J Taub
- G11 - INFORMATION STORAGE
Information Patent Application
TECHNIQUES TO MITIGATE BIAS DRIFT FOR A MEMORY DEVICE
- Publication number 20170287533
- Publication date Oct 5, 2017
- Intel Corporation
- Rakesh Jeyasingh
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL DEMARCATION VOLTAGE SENSING BEFORE WRITES
- Publication number 20170236580
- Publication date Aug 17, 2017
- Intel Corporation
- Daniel Chu
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS POINT MEMORY CONTROL
- Publication number 20170229172
- Publication date Aug 10, 2017
- Intel Corporation
- Raymond W. Zeng
- G11 - INFORMATION STORAGE
Information Patent Application
METHODS AND APPARATUSES FOR MODULATING THRESHOLD VOLTAGES OF MEMORY...
- Publication number 20170221536
- Publication date Aug 3, 2017
- Micron Technology, Inc.
- Davide Mantegazza
- G11 - INFORMATION STORAGE
Information Patent Application
TRANSIENT CURRENT-PROTECTED THRESHOLD SWITCHING DEVICES SYSTEMS AND...
- Publication number 20170186486
- Publication date Jun 29, 2017
- Intel Corporation
- Davide Mantegazza
- G11 - INFORMATION STORAGE
Information Patent Application
MULTISTAGE SET PROCEDURE FOR PHASE CHANGE MEMORY
- Publication number 20170169886
- Publication date Jun 15, 2017
- Intel Corporation
- Sanjay RANGAN
- G11 - INFORMATION STORAGE
Information Patent Application
CROSS POINT MEMORY CONTROL
- Publication number 20170076794
- Publication date Mar 16, 2017
- Intel Corporation
- Raymond W. Zeng
- G11 - INFORMATION STORAGE

Kiran PANGAL

Person

Patents Grantslast 30 patents

Modified write voltage for memory devices

Current delivery and spike mitigation in a memory cell array

Modified write voltage for memory devices

Techniques to mitigate error during a read operation to a memory array

Multi-level cell (MLC) cross-point memory

Dual demarcation voltage sensing before writes

Multi-level cell (MLC) techniques and circuits for cross-point memory

Reduced uncorrectable memory errors

Transient current-protected threshold switching devices systems and...

Multistage set procedure for phase change memory

Cross point memory control

Cross-point memory single-selection write technique

Dual demarcation voltage sensing before writes

Transient current-protected threshold switching devices systems and...

Multistage set procedure for phase change memory

Method and apparatus for multi-level setback read for three dimensi...

Apparatuses for modulating threshold voltages of memory cells

Method and apparatus for reducing silent data errors in non-volatil...

Reduced uncorrectable memory errors

Techniques to mitigate bias drift for a memory device

Managing disturbance induced errors

Cross point memory control

Error correction in memory

Cross-point memory single-selection write technique

Method and apparatus for multi-level setback read for three dimensi...

Techniques to mitigate bias drift for a memory device

Reduced uncorrectable memory errors

Methods and apparatuses for modulating threshold voltages of memory...

Multistage set procedure for phase change memory

Dynamic window to improve NAND endurance

Patents Applicationslast 30 patents

ENCODING ADDITIONAL STATES IN A THREE-DIMENSIONAL CROSSPOINT MEMORY...

CROSS-POINT MEMORY READ TECHNIQUE TO MITIGATE DRIFT ERRORS

MODIFIED WRITE VOLTAGE FOR MEMORY DEVICES

TECHNIQUES TO MITIGATE ERROR DURING A READ OPERATION TO A MEMORY ARRAY

MODIFIED WRITE VOLTAGE FOR MEMORY DEVICES

DUAL DEMARCATION VOLTAGE SENSING BEFORE WRITES

TRANSIENT CURRENT-PROTECTED THRESHOLD SWITCHING DEVICES SYSTEMS AND...

MULTISTAGE SET PROCEDURE FOR PHASE CHANGE MEMORY

REDUCED UNCORRECTABLE MEMORY ERRORS

METHOD AND APPARATUS FOR REDUCING SILENT DATA ERRORS IN NON-VOLATIL...

CROSS POINT MEMORY CONTROL

CROSS-POINT MEMORY SINGLE-SELECTION WRITE TECHNIQUE

TECHNIQUES TO MITIGATE BIAS DRIFT FOR A MEMORY DEVICE

CURRENT DELIVERY AND SPIKE MITIGATION IN A MEMORY CELL ARRAY

METHOD AND APPARATUS FOR MULTI-LEVEL SETBACK READ FOR THREE DIMENSI...

TRANSIENT CURRENT-PROTECTED THRESHOLD SWITCHING DEVICES SYSTEMS AND...

REDUCED UNCORRECTABLE MEMORY ERRORS

DYNAMIC WINDOW TO IMPROVE NAND ENDURANCE

METHOD AND APPARATUS FOR MULTI-LEVEL SETBACK READ FOR THREE DIMENSI...

MULTISTAGE SET PROCEDURE FOR PHASE CHANGE MEMORY

APPARATUSES FOR MODULATING THRESHOLD VOLTAGES OF MEMORY CELLS

MANAGING DISTURBANCE INDUCED ERRORS

CROSS-POINT MEMORY SINGLE-SELECTION WRITE TECHNIQUE

TECHNIQUES TO MITIGATE BIAS DRIFT FOR A MEMORY DEVICE

DUAL DEMARCATION VOLTAGE SENSING BEFORE WRITES

CROSS POINT MEMORY CONTROL

METHODS AND APPARATUSES FOR MODULATING THRESHOLD VOLTAGES OF MEMORY...

TRANSIENT CURRENT-PROTECTED THRESHOLD SWITCHING DEVICES SYSTEMS AND...

MULTISTAGE SET PROCEDURE FOR PHASE CHANGE MEMORY

CROSS POINT MEMORY CONTROL