Kishore K. Muchherla

Person

San Jose, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Conditional valley tracking during corrective reads
- Patent number 12,266,407
- Issue date Apr 1, 2025
- Micron Technology, Inc.
- Tomoharu Tanaka
- G11 - INFORMATION STORAGE
Information Patent Grant
Apparatus with non-linear delay variations for scheduling memory re...
- Patent number 12,249,364
- Issue date Mar 11, 2025
- Micron Technology, Inc.
- Huai-Yuan Tseng
- G11 - INFORMATION STORAGE
Information Patent Grant
Managing error-handling flows in memory devices
- Patent number 12,229,000
- Issue date Feb 18, 2025
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory device with dynamic cache management
- Patent number 12,216,573
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Parallelized defect detection across multiple sub-blocks in a memor...
- Patent number 12,217,799
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Paing Z. Htet
- G11 - INFORMATION STORAGE
Information Patent Grant
Adaptive read disturb scan
- Patent number 12,216,915
- Issue date Feb 4, 2025
- Micron Technology, Inc.
- Animesh R. Chowdhury
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory sub-system write sequence track
- Patent number 12,182,013
- Issue date Dec 31, 2024
- Micron Technology, Inc.
- Karl D. Schuh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Concurrent programming of retired wordline cells with dummy data
- Patent number 12,170,113
- Issue date Dec 17, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory sub-system media management groups
- Patent number 12,164,804
- Issue date Dec 10, 2024
- Micron Technology, Inc.
- Karl D. Schuh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory sub-system scan
- Patent number 12,148,484
- Issue date Nov 19, 2024
- Micron Technology, Inc.
- Vamsi Pavan Rayaprolu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory devices for multiple read operations
- Patent number 12,142,343
- Issue date Nov 12, 2024
- Micron Technology, Inc.
- Eric N. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Error correction in a memory device having an error correction code...
- Patent number 12,142,333
- Issue date Nov 12, 2024
- Micron Technology, Inc.
- Mustafa N. Kaynak
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory devices and systems including static and dynamic caches, and...
- Patent number 12,131,020
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Kishore K. Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Media management operations based on health characteristics of memo...
- Patent number 12,131,790
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Ashutosh Malshe
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Programming selective word lines during an erase operation in a mem...
- Patent number 12,131,028
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quick charge loss mitigation using two-pass controlled delay
- Patent number 12,131,060
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Read counter adjustment for delaying read disturb scans
- Patent number 12,131,788
- Issue date Oct 29, 2024
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Grant
Two-tier defect scan management
- Patent number 12,105,967
- Issue date Oct 1, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Copyback clear command for performing a scan and read in a memory d...
- Patent number 12,105,961
- Issue date Oct 1, 2024
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Code rate as function of logical saturation
- Patent number 12,099,725
- Issue date Sep 24, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduction of errors in data retrieved from a memory device to apply...
- Patent number 12,086,028
- Issue date Sep 10, 2024
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Buffer allocation for reducing block transit penalty
- Patent number 12,079,517
- Issue date Sep 3, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated command to calibrate read voltage level
- Patent number 12,073,891
- Issue date Aug 27, 2024
- Micron Technology, Inc.
- Eric N. Lee
- G11 - INFORMATION STORAGE
Information Patent Grant
Simplified operations to read memory cells coarsely programmed via...
- Patent number 12,073,892
- Issue date Aug 27, 2024
- Micron Technology, Inc.
- Phong Sy Nguyen
- G11 - INFORMATION STORAGE
Information Patent Grant
On-die cross-temperature management for a memory device
- Patent number 12,067,290
- Issue date Aug 20, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Two-pass corrective programming for memory cells that store multipl...
- Patent number 12,068,034
- Issue date Aug 20, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Voltage calibration scans to reduce memory device overhead
- Patent number 12,057,185
- Issue date Aug 6, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory block programming using defectivity information
- Patent number 12,051,479
- Issue date Jul 30, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Grant
Partitioned memory having error detection capability
- Patent number 12,026,052
- Issue date Jul 2, 2024
- Kishore K. Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Automatic wordline status bypass management
- Patent number 12,026,385
- Issue date Jul 2, 2024
- Micron Technology, Inc.
- Jiangang Wu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
MEMORY SUB-SYSTEM MEDIA MANAGEMENT GROUPS
- Publication number 20250103246
- Publication date Mar 27, 2025
- Micron Technology, Inc.
- Karl D. Schuh
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE WRITE PROGRAMMING FOR A SEGMENT OF A MEMORY DEVICE
- Publication number 20250077416
- Publication date Mar 6, 2025
- Micron Technology, Inc.
- Huai-Yuan Tseng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY MANAGEMENT AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING
- Publication number 20250077415
- Publication date Mar 6, 2025
- Micron Technology, Inc.
- Kishore K. Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONCURRENT PROGRAMMING OF RETIRED WORDLINE CELLS WITH DUMMY DATA
- Publication number 20250078932
- Publication date Mar 6, 2025
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G11 - INFORMATION STORAGE
Information Patent Application
PROGRAMMING SELECTIVE WORD LINES DURING AN ERASE OPERATION IN A MEM...
- Publication number 20250053301
- Publication date Feb 13, 2025
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY DEVICES FOR MULTIPLE READ OPERATIONS
- Publication number 20250029641
- Publication date Jan 23, 2025
- Micron Technology, Inc.
- Eric N. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICES AND SYSTEMS INCLUDING HYBRID CACHE, AND RELATED METHODS
- Publication number 20250013364
- Publication date Jan 9, 2025
- Micron Technology, Inc.
- Kishore K. Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUICK CHARGE LOSS MITIGATION USING TWO-PASS CONTROLLED DELAY
- Publication number 20250013382
- Publication date Jan 9, 2025
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANS
- Publication number 20250014655
- Publication date Jan 9, 2025
- Micron Technology, Inc.
- Nicola Ciocchini
- G11 - INFORMATION STORAGE
Information Patent Application
SENSE VOLTAGE ADJUSTMENT AMONG MULTIPLE ERASE BLOCKS
- Publication number 20250006275
- Publication date Jan 2, 2025
- Micron Technology, Inc.
- Shyam Sunder Raghunathan
- G11 - INFORMATION STORAGE
Information Patent Application
COPYBACK CLEAR COMMAND FOR PERFORMING A SCAN AND READ IN A MEMORY D...
- Publication number 20250004645
- Publication date Jan 2, 2025
- Micron Technology, Inc.
- Jeffrey S. McNeil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Reduction of Errors in Data Retrieved from a Memory Device to Apply...
- Publication number 20240419544
- Publication date Dec 19, 2024
- Micron Technology, Inc.
- Sivagnanam Parthasarathy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIMPLIFIED OPERATIONS TO READ MEMORY CELLS COARSELY PROGRAMMED VIA...
- Publication number 20240412792
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Phong Sy Nguyen
- G11 - INFORMATION STORAGE
Information Patent Application
CODE RATE AS FUNCTION OF LOGICAL SATURATION
- Publication number 20240411459
- Publication date Dec 12, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TWO-TIER DEFECT SCAN MANAGEMENT
- Publication number 20240402922
- Publication date Dec 5, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
BUFFER ALLOCATION FOR REDUCING BLOCK TRANSIT PENALTY
- Publication number 20240393980
- Publication date Nov 28, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
READ VOLTAGE LEVEL BIN SELECTION
- Publication number 20240395338
- Publication date Nov 28, 2024
- Micron Technology, Inc.
- Eric N. Lee
- G11 - INFORMATION STORAGE
Information Patent Application
ON-DIE CROSS-TEMPERATURE MANAGEMENT FOR A MEMORY DEVICE
- Publication number 20240370206
- Publication date Nov 7, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES FOR MANAGING A VOLTAGE RECOVERY OPERATION
- Publication number 20240371452
- Publication date Nov 7, 2024
- Micron Technology, Inc.
- Pitamber Shukla
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION
- Publication number 20240347128
- Publication date Oct 17, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G11 - INFORMATION STORAGE
Information Patent Application
READ PASS VOLTAGE ADJUSTMENT AMONG MULTIPLE ERASE BLOCKS COUPLED TO...
- Publication number 20240347126
- Publication date Oct 17, 2024
- Micron Technology, Inc.
- Akira Goda
- G11 - INFORMATION STORAGE
Information Patent Application
AUTOMATIC WORDLINE STATUS BYPASS MANAGEMENT
- Publication number 20240338138
- Publication date Oct 10, 2024
- Micron Technology, Inc.
- Jiangang Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PADDING CACHED DATA WITH VALID DATA FOR MEMORY FLUSH COMMANDS
- Publication number 20240311309
- Publication date Sep 19, 2024
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC SUPERBLOCK CONSTRUCTION
- Publication number 20240311029
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Kishore K. Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURING ERASE BLOCKS COUPLED TO A SAME STRING AS ZONES
- Publication number 20240311036
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Daniel J. Hubbard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMING ERASE BLOCKS COUPLED TO A SAME STRING
- Publication number 20240311057
- Publication date Sep 19, 2024
- Micron Technology, Inc.
- Daniel J. Hubbard
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTIPLE-PASS PROGRAMMING OF MEMORY CELLS USING TEMPORARY PARITY GE...
- Publication number 20240302999
- Publication date Sep 12, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ONE-LADDER READ OF MEMORY CELLS COARSELY PROGRAMMED VIA INTERLEAVED...
- Publication number 20240304250
- Publication date Sep 12, 2024
- Micron Technology, Inc.
- Phong Sy Nguyen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TOUCHUP FOR MEMORY DEVICE USING EMBEDDED ENCODER/DECODER
- Publication number 20240289218
- Publication date Aug 29, 2024
- Micron Technology, Inc.
- David Ebsen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WORKLOAD-BASED SCAN OPTIMIZATION
- Publication number 20240248646
- Publication date Jul 25, 2024
- Micron Technology, Inc.
- Kishore Kumar Muchherla
- G06 - COMPUTING CALCULATING COUNTING

Kishore K. Muchherla

Person

Patents Grantslast 30 patents

Conditional valley tracking during corrective reads

Apparatus with non-linear delay variations for scheduling memory re...

Managing error-handling flows in memory devices

Memory device with dynamic cache management

Parallelized defect detection across multiple sub-blocks in a memor...

Adaptive read disturb scan

Memory sub-system write sequence track

Concurrent programming of retired wordline cells with dummy data

Memory sub-system media management groups

Memory sub-system scan

Memory devices for multiple read operations

Error correction in a memory device having an error correction code...

Memory devices and systems including static and dynamic caches, and...

Media management operations based on health characteristics of memo...

Programming selective word lines during an erase operation in a mem...

Quick charge loss mitigation using two-pass controlled delay

Read counter adjustment for delaying read disturb scans

Two-tier defect scan management

Copyback clear command for performing a scan and read in a memory d...

Code rate as function of logical saturation

Reduction of errors in data retrieved from a memory device to apply...

Buffer allocation for reducing block transit penalty

Integrated command to calibrate read voltage level

Simplified operations to read memory cells coarsely programmed via...

On-die cross-temperature management for a memory device

Two-pass corrective programming for memory cells that store multipl...

Voltage calibration scans to reduce memory device overhead

Memory block programming using defectivity information

Partitioned memory having error detection capability

Automatic wordline status bypass management

Patents Applicationslast 30 patents

MEMORY SUB-SYSTEM MEDIA MANAGEMENT GROUPS

MULTIPLE WRITE PROGRAMMING FOR A SEGMENT OF A MEMORY DEVICE

MEMORY MANAGEMENT AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING

CONCURRENT PROGRAMMING OF RETIRED WORDLINE CELLS WITH DUMMY DATA

PROGRAMMING SELECTIVE WORD LINES DURING AN ERASE OPERATION IN A MEM...

MEMORY DEVICES FOR MULTIPLE READ OPERATIONS

MEMORY DEVICES AND SYSTEMS INCLUDING HYBRID CACHE, AND RELATED METHODS

QUICK CHARGE LOSS MITIGATION USING TWO-PASS CONTROLLED DELAY

READ COUNTER ADJUSTMENT FOR DELAYING READ DISTURB SCANS

SENSE VOLTAGE ADJUSTMENT AMONG MULTIPLE ERASE BLOCKS

COPYBACK CLEAR COMMAND FOR PERFORMING A SCAN AND READ IN A MEMORY D...

Reduction of Errors in Data Retrieved from a Memory Device to Apply...

SIMPLIFIED OPERATIONS TO READ MEMORY CELLS COARSELY PROGRAMMED VIA...

CODE RATE AS FUNCTION OF LOGICAL SATURATION

TWO-TIER DEFECT SCAN MANAGEMENT

BUFFER ALLOCATION FOR REDUCING BLOCK TRANSIT PENALTY

READ VOLTAGE LEVEL BIN SELECTION

ON-DIE CROSS-TEMPERATURE MANAGEMENT FOR A MEMORY DEVICE

TECHNIQUES FOR MANAGING A VOLTAGE RECOVERY OPERATION

MEMORY BLOCK PROGRAMMING USING DEFECTIVITY INFORMATION

READ PASS VOLTAGE ADJUSTMENT AMONG MULTIPLE ERASE BLOCKS COUPLED TO...

AUTOMATIC WORDLINE STATUS BYPASS MANAGEMENT

PADDING CACHED DATA WITH VALID DATA FOR MEMORY FLUSH COMMANDS

DYNAMIC SUPERBLOCK CONSTRUCTION

CONFIGURING ERASE BLOCKS COUPLED TO A SAME STRING AS ZONES

PROGRAMMING ERASE BLOCKS COUPLED TO A SAME STRING

MULTIPLE-PASS PROGRAMMING OF MEMORY CELLS USING TEMPORARY PARITY GE...

ONE-LADDER READ OF MEMORY CELLS COARSELY PROGRAMMED VIA INTERLEAVED...

TOUCHUP FOR MEMORY DEVICE USING EMBEDDED ENCODER/DECODER

WORKLOAD-BASED SCAN OPTIMIZATION