Ko-Ching Chao

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Hsinchu, TW

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Patents Grantslast 30 patents

Information Patent Grant
Physical interface and associated signal processing method for cloc...
- Patent number 11,935,577
- Issue date Mar 19, 2024
- Faraday Technology Corp.
- Sridhar Cheruku
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for performing divided-clock phase synchronization in multi-...
- Patent number 11,736,108
- Issue date Aug 22, 2023
- Faraday Technology Corp.
- Ko-Ching Chao
- G11 - INFORMATION STORAGE
Information Patent Grant
Gate signal control circuit for DDR memory system
- Patent number 11,360,709
- Issue date Jun 14, 2022
- Faraday Technology Corporation
- Hong-Yi Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for controlling multi-cycle write leveling process in memory...
- Patent number 11,145,343
- Issue date Oct 12, 2021
- Faraday Technology Corporation
- Sivaramakrishnan Subramanian
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHOD FOR PERFORMING SELF-CALIBRATION OF RECEIVER OF...
- Publication number 20240304268
- Publication date Sep 12, 2024
- FARADAY TECHNOLOGY CORP.
- Chih-Hung Wu
- G11 - INFORMATION STORAGE
Information Patent Application
PHYSICAL INTERFACE AND ASSOCIATED SIGNAL PROCESSING METHOD FOR CLOC...
- Publication number 20230253028
- Publication date Aug 10, 2023
- FARADAY TECHNOLOGY CORP.
- Sridhar Cheruku
- G11 - INFORMATION STORAGE
Information Patent Application
METHOD FOR PERFORMING DIVIDED-CLOCK PHASE SYNCHRONIZATION IN MULTI-...
- Publication number 20230231560
- Publication date Jul 20, 2023
- FARADAY TECHNOLOGY CORP.
- Ko-Ching Chao
- G11 - INFORMATION STORAGE
Information Patent Application
GATE SIGNAL CONTROL CIRCUIT FOR DDR MEMORY SYSTEM
- Publication number 20220164136
- Publication date May 26, 2022
- FARADAY TECHNOLOGY CORPORATION
- Hong-Yi WU
- G06 - COMPUTING CALCULATING COUNTING