Kolya Yastrebenetsky

Person

Boise, ID, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory cells with asymmetrical electrode interfaces
- Patent number 12,082,513
- Issue date Sep 3, 2024
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory device with double protective liner
- Patent number 11,647,638
- Issue date May 9, 2023
- Intel Corporation
- Anna Maria Conti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tapered memory cell profiles
- Patent number 11,545,625
- Issue date Jan 3, 2023
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cells having increased structural stability
- Patent number 11,367,833
- Issue date Jun 21, 2022
- Intel Corporation
- Pavan Kumar Reddy Aella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cells with asymmetrical electrode interfaces
- Patent number 11,133,463
- Issue date Sep 28, 2021
- Micron Technology, Inc.
- Agostino Pirovano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Tapered memory cell profiles
- Patent number 10,868,248
- Issue date Dec 15, 2020
- Micron Technology, Inc.
- Agostino Pirovano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cells with asymmetrical electrode interfaces
- Patent number 10,672,981
- Issue date Jun 2, 2020
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Grant
Dual-layer dielectric in memory device
- Patent number 10,629,652
- Issue date Apr 21, 2020
- Intel Corporation
- Michael J. Bernhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cells with asymmetrical electrode interfaces
- Patent number 10,541,364
- Issue date Jan 21, 2020
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Grant
Tapered memory cell profiles
- Patent number 10,424,730
- Issue date Sep 24, 2019
- Micron Technology, Inc.
- Agostino Pirovano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-layer dielectric in memory device
- Patent number 10,134,809
- Issue date Nov 20, 2018
- Intel Corporation
- Michael J. Bernhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Dual-layer dielectric in memory device
- Patent number 9,704,923
- Issue date Jul 11, 2017
- Intel Corporation
- Michael J. Bernhardt
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DIGIT LINE / CELL PLATE ISOLATION
- Publication number 20240407154
- Publication date Dec 5, 2024
- Micron Technology, Inc.
- Albert Daen Liao
Information Patent Application
CONTACT FORMATION FOR A MEMORY DEVICE
- Publication number 20240357837
- Publication date Oct 24, 2024
- Micron Technology, Inc.
- Darwin A. Clampitt
Information Patent Application
MEMORY CELLS HAVING INCREASED STRUCTURAL STABILITY
- Publication number 20220263019
- Publication date Aug 18, 2022
- Intel Corporation
- Pavan Kumar Reddy Aella
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELLS WITH ASYMMETRICAL ELECTRODE INTERFACES
- Publication number 20220059763
- Publication date Feb 24, 2022
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Application
TAPERED MEMORY CELL PROFILES
- Publication number 20210151673
- Publication date May 20, 2021
- Micron Technology, Inc.
- Agostino Pirovano
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELLS WITH ASYMMETRICAL ELECTRODE INTERFACES
- Publication number 20200321522
- Publication date Oct 8, 2020
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY DEVICE WITH DOUBLE PROTECTIVE LINER
- Publication number 20200286957
- Publication date Sep 10, 2020
- Anna Maria Conti
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELLS WITH ASYMMETRICAL ELECTRODE INTERFACES
- Publication number 20200119273
- Publication date Apr 16, 2020
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Application
TAPERED MEMORY CELL PROFILES
- Publication number 20200020855
- Publication date Jan 16, 2020
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Application
MEMORY CELLS WITH ASYMMETRICAL ELECTRODE INTERFACES
- Publication number 20190252606
- Publication date Aug 15, 2019
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Application
TAPERED MEMORY CELL PROFILES
- Publication number 20190252607
- Publication date Aug 15, 2019
- Micron Technology, Inc.
- Agostino Pirovano
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL-LAYER DIELECTRIC IN MEMORY DEVICE
- Publication number 20190206942
- Publication date Jul 4, 2019
- Intel Corporation
- Michael J. Bernhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MEMORY CELLS HAVING INCREASED STRUCTURAL STABILITY
- Publication number 20190044061
- Publication date Feb 7, 2019
- Intel Corporation
- Pavan Kumar Reddy Aella
- G11 - INFORMATION STORAGE
Information Patent Application
DUAL-LAYER DIELECTRIC IN MEMORY DEVICE
- Publication number 20170271412
- Publication date Sep 21, 2017
- Intel Corporation
- Michael J. Bernhardt
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Dual-layer dielectric in memory device
- Publication number 20170186815
- Publication date Jun 29, 2017
- Intel Corporation
- Michael J. Bernhardt
- H01 - BASIC ELECTRIC ELEMENTS

Kolya Yastrebenetsky

Person

Patents Grantslast 30 patents

Memory cells with asymmetrical electrode interfaces

Memory device with double protective liner

Tapered memory cell profiles

Memory cells having increased structural stability

Memory cells with asymmetrical electrode interfaces

Tapered memory cell profiles

Memory cells with asymmetrical electrode interfaces

Dual-layer dielectric in memory device

Memory cells with asymmetrical electrode interfaces

Tapered memory cell profiles

Dual-layer dielectric in memory device

Dual-layer dielectric in memory device

Patents Applicationslast 30 patents

DIGIT LINE / CELL PLATE ISOLATION

CONTACT FORMATION FOR A MEMORY DEVICE

MEMORY CELLS HAVING INCREASED STRUCTURAL STABILITY

MEMORY CELLS WITH ASYMMETRICAL ELECTRODE INTERFACES

TAPERED MEMORY CELL PROFILES

MEMORY CELLS WITH ASYMMETRICAL ELECTRODE INTERFACES

MEMORY DEVICE WITH DOUBLE PROTECTIVE LINER

MEMORY CELLS WITH ASYMMETRICAL ELECTRODE INTERFACES

TAPERED MEMORY CELL PROFILES

MEMORY CELLS WITH ASYMMETRICAL ELECTRODE INTERFACES

TAPERED MEMORY CELL PROFILES

DUAL-LAYER DIELECTRIC IN MEMORY DEVICE

MEMORY CELLS HAVING INCREASED STRUCTURAL STABILITY

DUAL-LAYER DIELECTRIC IN MEMORY DEVICE

Dual-layer dielectric in memory device