Konrad K. Lai

Person

Vancouver, WA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method for transactional memory and lock elision incl...
- Patent number 10,409,612
- Issue date Sep 10, 2019
- Intel Corporation
- Martin G. Dixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for transactional memory and lock elision incl...
- Patent number 10,409,611
- Issue date Sep 10, 2019
- Intel Corporation
- Martin G. Dixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tracking mode of a processing device in instruction tracing systems
- Patent number 10,331,452
- Issue date Jun 25, 2019
- Intel Corporation
- Thilo Schmitt
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic to test transactional execution status
- Patent number 10,261,879
- Issue date Apr 16, 2019
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic to test transactional execution status
- Patent number 10,248,524
- Issue date Apr 2, 2019
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic to test transactional execution status
- Patent number 10,223,227
- Issue date Mar 5, 2019
- Intel Corporation
- Ravi Rajwar
- G11 - INFORMATION STORAGE
Information Patent Grant
Instruction and logic to test transactional execution status
- Patent number 10,210,065
- Issue date Feb 19, 2019
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic to test transactional execution status
- Patent number 10,210,066
- Issue date Feb 19, 2019
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic to test transactional execution status
- Patent number 10,152,401
- Issue date Dec 11, 2018
- Intel Corporation
- Ravi Rajwar
- G11 - INFORMATION STORAGE
Information Patent Grant
Last branch record indicators for transactional memory
- Patent number 10,073,719
- Issue date Sep 11, 2018
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods and apparatus to manage speculative execution of object loc...
- Patent number 9,529,645
- Issue date Dec 27, 2016
- Intel Corporation
- Suresh Srinivas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Event counter checkpointing and restoring
- Patent number 9,372,764
- Issue date Jun 21, 2016
- Intel Corporation
- Laura A. Knauth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Last branch record register for storing taken branch information an...
- Patent number 9,354,878
- Issue date May 31, 2016
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Instruction and logic to test transactional execution status
- Patent number 9,268,596
- Issue date Feb 23, 2016
- Intel Corparation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus to bypass object lock by speculative execution...
- Patent number 8,972,994
- Issue date Mar 3, 2015
- Intel Corporation
- Suresh Srinivas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Event counter checkpointing and restoring
- Patent number 8,924,692
- Issue date Dec 30, 2014
- Intel Corporation
- Laura A. Knauth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Debugging parallel software using speculatively executed code seque...
- Patent number 8,881,106
- Issue date Nov 4, 2014
- Intel Corporation
- Peter Lachner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Last branch record indicators for transactional memory
- Patent number 8,782,382
- Issue date Jul 15, 2014
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processor with last branch record register storing transaction indi...
- Patent number 8,479,053
- Issue date Jul 2, 2013
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transactional memory in out-of-order processors with XABORT having...
- Patent number 8,301,849
- Issue date Oct 30, 2012
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transactional memory virtualization
- Patent number 8,180,967
- Issue date May 15, 2012
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Transactional memory in out-of-order processors
- Patent number 8,180,977
- Issue date May 15, 2012
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Identifying and processing essential and non-essential code separately
- Patent number 7,437,542
- Issue date Oct 14, 2008
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache line pre-load and pre-own based on cache coherence speculation
- Patent number 7,076,613
- Issue date Jul 11, 2006
- Intel Corporation
- Jih-Kwon Peir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Processing essential and non-essential code separately
- Patent number 7,020,766
- Issue date Mar 28, 2006
- Intel Corporation
- Hong Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hiding refresh of memory and refresh-hidden memory
- Patent number 6,757,784
- Issue date Jun 29, 2004
- Intel Corporation
- Shih-Lien L. Lu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache line pre-load and pre-own based on cache coherence speculation
- Patent number 6,725,341
- Issue date Apr 20, 2004
- Intel Corporation
- Jih-Kwon Peir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multiprocessor cache coherence management
- Patent number 6,711,662
- Issue date Mar 23, 2004
- Intel Corporation
- Jih-Kwon Peir
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing deferred transactions
- Patent number RE38388
- Issue date Jan 13, 2004
- Intel Corporation
- Nitin V. Sarangdhar
- 710 - Electrical computers and digital data processing systems: input/output
Information Patent Grant
Modified least recently allocated cache replacement method and appa...
- Patent number 6,671,780
- Issue date Dec 30, 2003
- Intel Corporation
- Shih-Lien L. Lu
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
SYSTEM FOR SPECULATIVE EXECUTION EVENT COUNTER CHECKPOINTING AND RE...
- Publication number 20170235580
- Publication date Aug 17, 2017
- Intel Corporation
- Laura A. Knauth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM-ON-CHIP FOR SPECULATIVE EXECUTION EVENT COUNTER CHECKPOINTIN...
- Publication number 20170235638
- Publication date Aug 17, 2017
- Intel Corporation
- Laura A. Knauth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROCESSOR FOR SPECULATIVE EXECUTION EVENT COUNTER CHECKPOINTING AND...
- Publication number 20170235579
- Publication date Aug 17, 2017
- Intel Corporation
- Laura A. Knauth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and logic to test transactional execution status
- Publication number 20160266992
- Publication date Sep 15, 2016
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, apparatus, and system for speculative abort control mechanisms
- Publication number 20160246606
- Publication date Aug 25, 2016
- Martin G. Dixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR SPECULATIVE ABORT CONTROL MECHANISMS
- Publication number 20160239304
- Publication date Aug 18, 2016
- Martin G. Dixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Last Branch Record Indicators For Transactional Memory
- Publication number 20160232041
- Publication date Aug 11, 2016
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, apparatus, and system for speculative abort control mechanisms
- Publication number 20160210177
- Publication date Jul 21, 2016
- Martin G. Dixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and logic to test transactional execution status
- Publication number 20160202987
- Publication date Jul 14, 2016
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction And Logic To Test Transactional Execution Status
- Publication number 20160202979
- Publication date Jul 14, 2016
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and logic to test transactional execution status
- Publication number 20160203019
- Publication date Jul 14, 2016
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and logic to test transactional execution status
- Publication number 20160203068
- Publication date Jul 14, 2016
- Intel Corporation
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC TO TEST TRANSACTIONAL EXECUTION STATUS
- Publication number 20160188479
- Publication date Jun 30, 2016
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, apparatus, and system for speculative abort control mechanisms
- Publication number 20160154648
- Publication date Jun 2, 2016
- Martin G. Dixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, apparatus, and system for speculative abort control mechanisms
- Publication number 20160132335
- Publication date May 12, 2016
- Martin G. Dixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, apparaturs, and system for speculative abort control mechan...
- Publication number 20160132334
- Publication date May 12, 2016
- Martin G. Dixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, apparatus, and system for speculative abort control mechanisms
- Publication number 20160132337
- Publication date May 12, 2016
- Martin G. Dixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, Apparatus, And System For Speculative Abort Control Mechanisms
- Publication number 20160132333
- Publication date May 12, 2016
- Martin G. Dixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, apparatus, and system for speculative abort control mechanisms
- Publication number 20160132336
- Publication date May 12, 2016
- Martin G. Dixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS TO BYPASS OBJECT LOCKS
- Publication number 20150169384
- Publication date Jun 18, 2015
- Intel Corporation
- Suresh Srinivas
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EVENT COUNTER CHECKPOINTING AND RESTORING
- Publication number 20150089286
- Publication date Mar 26, 2015
- Laura A. Knauth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL...
- Publication number 20150032998
- Publication date Jan 29, 2015
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TRACKING MODE OF A PROCESSING DEVICE IN INSTRUCTION TRACING SYSTEMS
- Publication number 20150006717
- Publication date Jan 1, 2015
- Thilo Schmitt
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL...
- Publication number 20140379996
- Publication date Dec 25, 2014
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Last Branch Record Indicators For Transactional Memory
- Publication number 20140258695
- Publication date Sep 11, 2014
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR SPECULATIVE ABORT CONTROL MECHANISMS
- Publication number 20140059333
- Publication date Feb 27, 2014
- Martin G. Dixon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC TO TEST TRANSACTIONAL EXECUTION STATUS
- Publication number 20130205119
- Publication date Aug 8, 2013
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAST BRANCH RECORD INDICATORS FOR TRANSACTIONAL MEMORY
- Publication number 20130179668
- Publication date Jul 11, 2013
- RAVI RAJWAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS, AND SYSTEM FOR SPECULATIVE EXECUTION EVENT COUNT...
- Publication number 20120227045
- Publication date Sep 6, 2012
- Laura A. Knauth
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LAST BRANCH RECORD INDICATORS FOR TRANSACTIONAL MEMORY
- Publication number 20120030518
- Publication date Feb 2, 2012
- Ravi Rajwar
- G06 - COMPUTING CALCULATING COUNTING

Konrad K. Lai

Person

Patents Grantslast 30 patents

Apparatus and method for transactional memory and lock elision incl...

Apparatus and method for transactional memory and lock elision incl...

Tracking mode of a processing device in instruction tracing systems

Instruction and logic to test transactional execution status

Instruction and logic to test transactional execution status

Instruction and logic to test transactional execution status

Instruction and logic to test transactional execution status

Instruction and logic to test transactional execution status

Instruction and logic to test transactional execution status

Last branch record indicators for transactional memory

Methods and apparatus to manage speculative execution of object loc...

Event counter checkpointing and restoring

Last branch record register for storing taken branch information an...

Instruction and logic to test transactional execution status

Method and apparatus to bypass object lock by speculative execution...

Event counter checkpointing and restoring

Debugging parallel software using speculatively executed code seque...

Last branch record indicators for transactional memory

Processor with last branch record register storing transaction indi...

Transactional memory in out-of-order processors with XABORT having...

Transactional memory virtualization

Transactional memory in out-of-order processors

Identifying and processing essential and non-essential code separately

Cache line pre-load and pre-own based on cache coherence speculation

Processing essential and non-essential code separately

Hiding refresh of memory and refresh-hidden memory

Cache line pre-load and pre-own based on cache coherence speculation

Multiprocessor cache coherence management

Method and apparatus for performing deferred transactions

Modified least recently allocated cache replacement method and appa...

Patents Applicationslast 30 patents

SYSTEM FOR SPECULATIVE EXECUTION EVENT COUNTER CHECKPOINTING AND RE...

SYSTEM-ON-CHIP FOR SPECULATIVE EXECUTION EVENT COUNTER CHECKPOINTIN...

PROCESSOR FOR SPECULATIVE EXECUTION EVENT COUNTER CHECKPOINTING AND...

Instruction and logic to test transactional execution status

Method, apparatus, and system for speculative abort control mechanisms

METHOD, APPARATUS, AND SYSTEM FOR SPECULATIVE ABORT CONTROL MECHANISMS

Last Branch Record Indicators For Transactional Memory

Method, apparatus, and system for speculative abort control mechanisms

Instruction and logic to test transactional execution status

Instruction And Logic To Test Transactional Execution Status

Instruction and logic to test transactional execution status

Instruction and logic to test transactional execution status

INSTRUCTION AND LOGIC TO TEST TRANSACTIONAL EXECUTION STATUS

Method, apparatus, and system for speculative abort control mechanisms

Method, apparatus, and system for speculative abort control mechanisms

Method, apparaturs, and system for speculative abort control mechan...

Method, apparatus, and system for speculative abort control mechanisms

Method, Apparatus, And System For Speculative Abort Control Mechanisms

Method, apparatus, and system for speculative abort control mechanisms

METHODS AND APPARATUS TO BYPASS OBJECT LOCKS

EVENT COUNTER CHECKPOINTING AND RESTORING

METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL...

TRACKING MODE OF A PROCESSING DEVICE IN INSTRUCTION TRACING SYSTEMS

METHOD, APPARATUS, AND SYSTEM FOR TRANSACTIONAL SPECULATION CONTROL...

Last Branch Record Indicators For Transactional Memory

METHOD, APPARATUS, AND SYSTEM FOR SPECULATIVE ABORT CONTROL MECHANISMS

INSTRUCTION AND LOGIC TO TEST TRANSACTIONAL EXECUTION STATUS

LAST BRANCH RECORD INDICATORS FOR TRANSACTIONAL MEMORY

METHOD, APPARATUS, AND SYSTEM FOR SPECULATIVE EXECUTION EVENT COUNT...

LAST BRANCH RECORD INDICATORS FOR TRANSACTIONAL MEMORY