Konstantine Karavakis

Person

Pleasanton, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Electroless and electrolytic deposition process for forming traces...
- Patent number 11,653,453
- Issue date May 16, 2023
- CATLAM, LLC
- Kenneth S Bahl
- C08 - ORGANIC MACROMOLECULAR COMPOUNDS THEIR PREPARATION OR CHEMICAL WORKING-...
Information Patent Grant
Process for fabrication of a printed circuit board using a semi-add...
- Patent number 11,638,354
- Issue date Apr 25, 2023
- CATLAM, LLC
- Kenneth S. Bahl
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Catalytic laminate with conductive traces formed during lamination
- Patent number 11,477,893
- Issue date Oct 18, 2022
- CATLAM, LLC
- Kenneth S Bahl
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Circuit board using non-catalytic laminate with catalytic adhesive...
- Patent number 10,959,329
- Issue date Mar 23, 2021
- CATLAM, LLC
- Kenneth S. Bahl
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Process for forming traces on a catalytic laminate
- Patent number 10,849,233
- Issue date Nov 24, 2020
- CATLAM, LLC
- Kenneth S Bahl
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Catalytic laminate with conductive traces formed during lamination
- Patent number 10,827,624
- Issue date Nov 3, 2020
- CATLAM, LLC
- Kenneth S Bahl
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Catalytic circuit board with traces and vias
- Patent number 10,806,029
- Issue date Oct 13, 2020
- CATLAM, LLC
- Kenneth S. Bahl
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Process for printed circuit boards using backing foil
- Patent number 10,765,012
- Issue date Sep 1, 2020
- CATLAM, LLC
- Kenneth S. Bahl
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method for making a multi-layer circuit board using conductive past...
- Patent number 10,765,003
- Issue date Sep 1, 2020
- CATLAM, LLC
- Kenneth S. Bahl
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method and apparatus for forming contacts on an integrated circuit...
- Patent number 10,685,931
- Issue date Jun 16, 2020
- CATLAM LLC
- Kenneth S. Bahl
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Method for wafer level packaging
- Patent number 10,573,610
- Issue date Feb 25, 2020
- CATLAM, LLC
- Kenneth S. Bahl
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Multi-layer circuit board using interposer layer and conductive paste
- Patent number 10,349,520
- Issue date Jul 9, 2019
- CATLAM, LLC
- Konstantine Karavakis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Circuit board with catalytic adhesive
- Patent number 10,306,756
- Issue date May 28, 2019
- Sierra Circuits, Inc.
- Kenneth S. Bahl
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Circuit board apparatus and method
- Patent number 9,942,981
- Issue date Apr 10, 2018
- Sierra Circuits, Inc.
- Kenneth S. Bahl
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Integrated circuit wafer integration with catalytic laminate or adh...
- Patent number 9,922,951
- Issue date Mar 20, 2018
- Sierra Circuits, Inc.
- Kenneth S. Bahl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Catalytic laminate apparatus and method
- Patent number 9,706,650
- Issue date Jul 11, 2017
- Sierra Circuits, Inc.
- Kenneth S. Bahl
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Via in a printed circuit board
- Patent number 9,706,667
- Issue date Jul 11, 2017
- Sierra Circuits, Inc.
- Konstantine Karavakis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Via in a printed circuit board
- Patent number 9,674,967
- Issue date Jun 6, 2017
- Sierra Circuits, Inc.
- Konstantine Karavakis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods for forming embedded traces
- Patent number 9,631,279
- Issue date Apr 25, 2017
- Sierra Circuits, Inc.
- Kenneth S. Bahl
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Via in a printed circuit board
- Patent number 9,398,703
- Issue date Jul 19, 2016
- Sierra Circuits, Inc.
- Konstantine Karavakis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Method for forming traces of a printed circuit board
- Patent number 9,380,700
- Issue date Jun 28, 2016
- Sierra Circuits, Inc.
- Konstantine Karavakis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Grant
Methods of making compliant semiconductor chip packages
- Patent number 8,558,386
- Issue date Oct 15, 2013
- Tessera, Inc.
- Joseph Fjelstad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Microelectronic assemblies having compliant layers
- Patent number 8,338,925
- Issue date Dec 25, 2012
- Tessera, Inc.
- Joseph Fjelstad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Probe head apparatus for testing semiconductors
- Patent number 8,004,296
- Issue date Aug 23, 2011
- Centipede Systems, Inc.
- Peter T. Di Stefano
- G01 - MEASURING TESTING
Information Patent Grant
Microelectronic assemblies having compliant layers
- Patent number 7,872,344
- Issue date Jan 18, 2011
- Tessera, Inc.
- Joseph Fjelstad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Compliant thermal contactor
- Patent number 7,834,447
- Issue date Nov 16, 2010
- Centipede Systems, Inc.
- Konstantine N. Karavakis
- G01 - MEASURING TESTING
Information Patent Grant
Compliant thermal contactor
- Patent number 7,719,816
- Issue date May 18, 2010
- Centipede Systems, Inc.
- Konstantine N. Karavakis
- G01 - MEASURING TESTING
Information Patent Grant
Self-cleaning socket for microelectronic devices
- Patent number 7,491,069
- Issue date Feb 17, 2009
- Centipede Systems, Inc.
- Thomas H. Di Stefano
- G01 - MEASURING TESTING
Information Patent Grant
Microelectronic assemblies having compliant layers
- Patent number 7,408,260
- Issue date Aug 5, 2008
- Tessera, Inc.
- Joseph Fjelstad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Connecting a probe card and an interposer using a compliant connector
- Patent number 7,170,306
- Issue date Jan 30, 2007
- Celerity Research, Inc.
- Konstantine N. Karavakis
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
Semi-Additive Process for Printed Circuit Boards
- Publication number 20230247774
- Publication date Aug 3, 2023
- CATLAM, LLC
- Kenneth S. BAHL
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Process For Forming Traces on a Catalytic Laminate
- Publication number 20210051804
- Publication date Feb 18, 2021
- CATLAM, LLC
- Kenneth S. BAHL
- C08 - ORGANIC MACROMOLECULAR COMPOUNDS THEIR PREPARATION OR CHEMICAL WORKING-...
Information Patent Application
Catalytic Laminate with Conductive Traces formed during Lamination
- Publication number 20210022252
- Publication date Jan 21, 2021
- CATLAM LLC
- Kenneth S BAHL
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Circuit Board using non-catalytic laminate with catalytic adhesive...
- Publication number 20200404785
- Publication date Dec 24, 2020
- CATLAM, LLC
- Kenneth S. BAHL
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Systems and Methods of Manufacturing Circuit Boards
- Publication number 20200389980
- Publication date Dec 10, 2020
- OSI Electronics, Inc.
- Konstantine Karavakis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Semi-Additive Process for Printed Circuit Boards
- Publication number 20200389983
- Publication date Dec 10, 2020
- CATLAM LLC
- Kenneth S. BAHL
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Folded Multilayered Flexible Circuit Board and Methods of Manufactu...
- Publication number 20200296840
- Publication date Sep 17, 2020
- OSI Electronics, Inc.
- Konstantine Karavakis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Circuit Board with Improved Thermal, Moisture Resistance, and Elect...
- Publication number 20200288570
- Publication date Sep 10, 2020
- OSI Electronics, Inc.
- Robert Jung
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Circuit Board with Improved Thermal, Moisture Resistance, and Elect...
- Publication number 20200288569
- Publication date Sep 10, 2020
- OSI Electronics, Inc.
- Robert Jung
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
UV curable Catalytic Adhesive for Circuit Boards with Traces and Vias
- Publication number 20200008306
- Publication date Jan 2, 2020
- SIERRA CIRCUITS, INC.
- Konstantine KARAVAKIS
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method for making a Multi-Layer Circuit Board using conductive Past...
- Publication number 20190320530
- Publication date Oct 17, 2019
- CATLAM, LLC
- Kenneth S. BAHL
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Catalytic Laminate with Conductive Traces formed during Lamination
- Publication number 20190274221
- Publication date Sep 5, 2019
- SIERRA CIRCUITS, INC.
- Kenneth S. BAHL
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
Catalytic Laminate Apparatus and Method
- Publication number 20190239349
- Publication date Aug 1, 2019
- SIERRA CIRCUITS, INC.
- Kenneth S. Bahl
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Plasma Etched Catalytic Laminate with Traces and Vias
- Publication number 20190014666
- Publication date Jan 10, 2019
- SIERRA CIRCUITS, INC.
- Kenneth S. BAHL
- C08 - ORGANIC MACROMOLECULAR COMPOUNDS THEIR PREPARATION OR CHEMICAL WORKING-...
Information Patent Application
Semi-additive process for printed circuit boards
- Publication number 20190014667
- Publication date Jan 10, 2019
- SIERRA CIRCUITS, INC.
- Kenneth S. Bahl
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Multi-Layer Circuit Board using Interposer layer and Conductive Paste
- Publication number 20190008044
- Publication date Jan 3, 2019
- SIERRA CIRCUITS, INC.
- Konstantine Karavakis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Circuit board with Catalytic Adhesive
- Publication number 20180168036
- Publication date Jun 14, 2018
- SIERRA CIRCUITS, INC.
- Kenneth S. Bahl
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
Method and Apparatus for forming Contacts on an Integrated Circuit...
- Publication number 20180158793
- Publication date Jun 7, 2018
- SIERRA CIRCUITS, INC.
- Kenneth S. Bahl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Circuit Board Apparatus and Method
- Publication number 20180054889
- Publication date Feb 22, 2018
- Sierra Circuits, Inc.
- Kenneth S. Bahl
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
VIA IN A PRINTED CIRCUIT BOARD
- Publication number 20160295708
- Publication date Oct 6, 2016
- SIERRA CIRCUITS, INC.
- Konstantine Karavakis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
PRINTED CIRCUIT BOARD
- Publication number 20160278206
- Publication date Sep 22, 2016
- SIERRA CIRCUITS, INC.
- Kenneth S. Bahl
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
WAFER LEVEL PACKAGING USING A CATALYTIC ADHESIVE
- Publication number 20160148893
- Publication date May 26, 2016
- SIERRA CIRCUITS, INC.
- Kenneth S. Bahl
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VIA IN A PRINTED CIRCUIT BOARD
- Publication number 20160135297
- Publication date May 12, 2016
- SIERRA CIRCUITS, INC.
- Konstantine Karavakis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
EMBEDDED TRACES
- Publication number 20150334826
- Publication date Nov 19, 2015
- Konstantine Karavakis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
VIA IN A PRINTED CIRCUIT BOARD
- Publication number 20150334836
- Publication date Nov 19, 2015
- Konstantine Karavakis
- H05 - ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
Information Patent Application
EMBEDDED TRACES
- Publication number 20150334825
- Publication date Nov 19, 2015
- Kenneth S. Bahl
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
METHODS OF MAKING COMPLIANT SEMICONDUCTOR CHIP PACKAGES
- Publication number 20150194347
- Publication date Jul 9, 2015
- Tessera, Inc.
- Joseph Fjelstad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF MAKING COMPLIANT SEMICONDUCTOR CHIP PACKAGES
- Publication number 20140042634
- Publication date Feb 13, 2014
- Tessera, Inc.
- Joseph Fjelstad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MICROELECTRONIC ASSEMBLIES HAVING COMPLIANT LAYERS
- Publication number 20110095441
- Publication date Apr 28, 2011
- Tessera, Inc.
- Joseph Fjelstad
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Probe Head Apparatus for Testing Semiconductors
- Publication number 20100045322
- Publication date Feb 25, 2010
- Centipede Systems, Inc.
- Peter T. Di Stefano
- G01 - MEASURING TESTING

Konstantine Karavakis

Person

Patents Grantslast 30 patents

Electroless and electrolytic deposition process for forming traces...

Process for fabrication of a printed circuit board using a semi-add...

Catalytic laminate with conductive traces formed during lamination

Circuit board using non-catalytic laminate with catalytic adhesive...

Process for forming traces on a catalytic laminate

Catalytic laminate with conductive traces formed during lamination

Catalytic circuit board with traces and vias

Process for printed circuit boards using backing foil

Method for making a multi-layer circuit board using conductive past...

Method and apparatus for forming contacts on an integrated circuit...

Method for wafer level packaging

Multi-layer circuit board using interposer layer and conductive paste

Circuit board with catalytic adhesive

Circuit board apparatus and method

Integrated circuit wafer integration with catalytic laminate or adh...

Catalytic laminate apparatus and method

Via in a printed circuit board

Via in a printed circuit board

Methods for forming embedded traces

Via in a printed circuit board

Method for forming traces of a printed circuit board

Methods of making compliant semiconductor chip packages

Microelectronic assemblies having compliant layers

Probe head apparatus for testing semiconductors

Microelectronic assemblies having compliant layers

Compliant thermal contactor

Compliant thermal contactor

Self-cleaning socket for microelectronic devices

Microelectronic assemblies having compliant layers

Connecting a probe card and an interposer using a compliant connector

Patents Applicationslast 30 patents

Semi-Additive Process for Printed Circuit Boards

Process For Forming Traces on a Catalytic Laminate

Catalytic Laminate with Conductive Traces formed during Lamination

Circuit Board using non-catalytic laminate with catalytic adhesive...

Systems and Methods of Manufacturing Circuit Boards

Semi-Additive Process for Printed Circuit Boards

Folded Multilayered Flexible Circuit Board and Methods of Manufactu...

Circuit Board with Improved Thermal, Moisture Resistance, and Elect...

Circuit Board with Improved Thermal, Moisture Resistance, and Elect...

UV curable Catalytic Adhesive for Circuit Boards with Traces and Vias

Method for making a Multi-Layer Circuit Board using conductive Past...

Catalytic Laminate with Conductive Traces formed during Lamination

Catalytic Laminate Apparatus and Method

Plasma Etched Catalytic Laminate with Traces and Vias

Semi-additive process for printed circuit boards

Multi-Layer Circuit Board using Interposer layer and Conductive Paste

Circuit board with Catalytic Adhesive

Method and Apparatus for forming Contacts on an Integrated Circuit...

Circuit Board Apparatus and Method

VIA IN A PRINTED CIRCUIT BOARD

PRINTED CIRCUIT BOARD

WAFER LEVEL PACKAGING USING A CATALYTIC ADHESIVE

VIA IN A PRINTED CIRCUIT BOARD

EMBEDDED TRACES

VIA IN A PRINTED CIRCUIT BOARD

EMBEDDED TRACES

METHODS OF MAKING COMPLIANT SEMICONDUCTOR CHIP PACKAGES

METHODS OF MAKING COMPLIANT SEMICONDUCTOR CHIP PACKAGES

MICROELECTRONIC ASSEMBLIES HAVING COMPLIANT LAYERS

Probe Head Apparatus for Testing Semiconductors