Koushik Banerjee

Person

Milpitas, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Configurable resistivity for lines in a memory device
- Patent number 12,040,014
- Issue date Jul 16, 2024
- Micron Technology, Inc.
- Koushik Banerjee
- G11 - INFORMATION STORAGE
Information Patent Grant
Modified write voltage for memory devices
- Patent number 11,705,197
- Issue date Jul 18, 2023
- Micron Technology, Inc.
- Sandeepan Dasgupta
- G11 - INFORMATION STORAGE
Information Patent Grant
Configurable resistivity for lines in a memory device
- Patent number 11,495,293
- Issue date Nov 8, 2022
- Micron Technology, Inc.
- Koushik Banerjee
- G11 - INFORMATION STORAGE
Information Patent Grant
Modified write voltage for memory devices
- Patent number 11,170,853
- Issue date Nov 9, 2021
- Micron Technology, Inc.
- Sandeepan Dasgupta
- G11 - INFORMATION STORAGE
Information Patent Grant
Non volatile cross point memory having word line pass transistor wi...
- Patent number 11,100,984
- Issue date Aug 24, 2021
- Intel Corporation
- Koushik Banerjee
- G11 - INFORMATION STORAGE
Information Patent Grant
Set technique for phase change memory
- Patent number 10,884,640
- Issue date Jan 5, 2021
- Intel Corporation
- Koushik Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tailoring current magnitude and duration during a programming pulse...
- Patent number 10,796,761
- Issue date Oct 6, 2020
- Intel Corporation
- Koushik Banerjee
- G11 - INFORMATION STORAGE
Information Patent Grant
Tailoring timing offsets during a programming pulse for a memory de...
- Patent number 10,553,286
- Issue date Feb 4, 2020
- Intel Corporation
- Koushik Banerjee
- G11 - INFORMATION STORAGE
Information Patent Grant
Tailoring current magnitude and duration during a programming pulse...
- Patent number 10,360,977
- Issue date Jul 23, 2019
- Intel Corporation
- Koushik Banerjee
- G11 - INFORMATION STORAGE
Information Patent Grant
Set technique for phase change memory
- Patent number 10,248,351
- Issue date Apr 2, 2019
- Intel Corporation
- Koushik Banerjee
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CONFIGURABLE RESISTIVITY FOR LINES IN A MEMORY DEVICE
- Publication number 20240379157
- Publication date Nov 14, 2024
- Micron Technology, Inc.
- Koushik Banerjee
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURABLE RESISTIVITY FOR LINES IN A MEMORY DEVICE
- Publication number 20230114440
- Publication date Apr 13, 2023
- Micron Technology, Inc.
- Koushik Banerjee
- G11 - INFORMATION STORAGE
Information Patent Application
MODIFIED WRITE VOLTAGE FOR MEMORY DEVICES
- Publication number 20220068385
- Publication date Mar 3, 2022
- Micron Technology, Inc.
- Sandeepan Dasgupta
- G11 - INFORMATION STORAGE
Information Patent Application
MODIFIED WRITE VOLTAGE FOR MEMORY DEVICES
- Publication number 20210280244
- Publication date Sep 9, 2021
- Micron Technology, Inc.
- Sandeepan Dasgupta
- G11 - INFORMATION STORAGE
Information Patent Application
CONFIGURABLE RESISTIVITY FOR LINES IN A MEMORY DEVICE
- Publication number 20210241828
- Publication date Aug 5, 2021
- Micron Technology, Inc.
- Koushik Banerjee
- G11 - INFORMATION STORAGE
Information Patent Application
NON VOLATILE CROSS POINT MEMORY HAVING WORD LINE PASS TRANSISTOR WI...
- Publication number 20210225444
- Publication date Jul 22, 2021
- Intel Corporation
- Koushik BANERJEE
- G11 - INFORMATION STORAGE
Information Patent Application
TAILORING CURRENT MAGNITUDE AND DURATION DURING A PROGRAMMING PULSE...
- Publication number 20190348114
- Publication date Nov 14, 2019
- Intel Corporation
- Koushik Banerjee
- G11 - INFORMATION STORAGE
Information Patent Application
SET TECHNIQUE FOR PHASE CHANGE MEMORY
- Publication number 20190324671
- Publication date Oct 24, 2019
- Intel Corporation
- Koushik Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO MITIGATE SELECTION FAILURE FOR A MEMORY DEVICE
- Publication number 20190206491
- Publication date Jul 4, 2019
- Intel Corporation
- Koushik BANERJEE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SET TECHNIQUE FOR PHASE CHANGE MEMORY
- Publication number 20190102099
- Publication date Apr 4, 2019
- Intel Corporation
- Koushik Banerjee
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAILORING CURRENT MAGNITUDE AND DURATION DURING A PROGRAMMING PULSE...
- Publication number 20190043576
- Publication date Feb 7, 2019
- Intel Corporation
- Koushik Banerjee
- G11 - INFORMATION STORAGE
Information Patent Application
TAILORING TIMING OFFSETS DURING A PROGRAMMING PULSE FOR A MEMORY DE...
- Publication number 20190043585
- Publication date Feb 7, 2019
- Intel Corporation
- Koushik Banerjee
- G11 - INFORMATION STORAGE

Koushik Banerjee

Person

Patents Grantslast 30 patents

Configurable resistivity for lines in a memory device

Modified write voltage for memory devices

Configurable resistivity for lines in a memory device

Modified write voltage for memory devices

Non volatile cross point memory having word line pass transistor wi...

Set technique for phase change memory

Tailoring current magnitude and duration during a programming pulse...

Tailoring timing offsets during a programming pulse for a memory de...

Tailoring current magnitude and duration during a programming pulse...

Set technique for phase change memory

Patents Applicationslast 30 patents

CONFIGURABLE RESISTIVITY FOR LINES IN A MEMORY DEVICE

CONFIGURABLE RESISTIVITY FOR LINES IN A MEMORY DEVICE

MODIFIED WRITE VOLTAGE FOR MEMORY DEVICES

MODIFIED WRITE VOLTAGE FOR MEMORY DEVICES

CONFIGURABLE RESISTIVITY FOR LINES IN A MEMORY DEVICE

NON VOLATILE CROSS POINT MEMORY HAVING WORD LINE PASS TRANSISTOR WI...

TAILORING CURRENT MAGNITUDE AND DURATION DURING A PROGRAMMING PULSE...

SET TECHNIQUE FOR PHASE CHANGE MEMORY

TECHNIQUES TO MITIGATE SELECTION FAILURE FOR A MEMORY DEVICE

SET TECHNIQUE FOR PHASE CHANGE MEMORY

TAILORING CURRENT MAGNITUDE AND DURATION DURING A PROGRAMMING PULSE...

TAILORING TIMING OFFSETS DURING A PROGRAMMING PULSE FOR A MEMORY DE...