Krishna Prasad Belkhale

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Method, system, and product for deferred merge based method for gra...
- Patent number 11,188,696
- Issue date Nov 30, 2021
- Cadence Design Systems, Inc.
- Amit Dhuria
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, system, and product for an improved approach to placement a...
- Patent number 11,144,698
- Issue date Oct 12, 2021
- Cadence Design Systems, Inc.
- Vibhor Garg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods, systems, and articles of manufacture for multi-mode, multi...
- Patent number 10,133,842
- Issue date Nov 20, 2018
- Cadence Design Systems, Inc.
- Pawan Kulshreshtha
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for guiding remedial transformations of a circuit...
- Patent number 8,788,995
- Issue date Jul 22, 2014
- Cadence Design Systems, Inc.
- Naresh Kumar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for common path pessimism reduction in timing ana...
- Patent number 8,745,561
- Issue date Jun 3, 2014
- Cadence Design Systems, Inc.
- Vibhor Garg
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing an analytical wirelength formula...
- Patent number 7,797,649
- Issue date Sep 14, 2010
- Cadence Design Systems, Inc.
- Hussein Etawil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Assertion handling for timing model extraction
- Patent number 7,356,451
- Issue date Apr 8, 2008
- Cadence Design Systems, Inc.
- Cho Woo Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing an analytical wirelength formula...
- Patent number 7,168,053
- Issue date Jan 23, 2007
- Cadence Design Systems, Inc.
- Hussein Etawil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for implementing an analytical wirelength formula...
- Patent number 7,107,556
- Issue date Sep 12, 2006
- Cadence Design Systems, Inc.
- Hussein Etawil
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Timing model extraction by timing graph reduction
- Patent number 6,928,630
- Issue date Aug 9, 2005
- Cadence Design Systems, Inc.
- Cho Woo Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay estimation for restructuring
- Patent number 6,672,776
- Issue date Jan 6, 2004
- Cadence Design Systems
- Johnson Chan Limqueco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Delay estimation for restructuring the technology independent circuit
- Patent number 6,543,037
- Issue date Apr 1, 2003
- Cadence Design Systems, Inc.
- Johnson Chan Limqueco
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for performing both negative and positive slac...
- Patent number 6,401,231
- Issue date Jun 4, 2002
- Cadence Design Systems, Inc.
- Krishna Belkhale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cluster matching for circuit implementation
- Patent number 6,023,566
- Issue date Feb 8, 2000
- Cadence Design Systems
- Krishna Belkhale
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cluster determination for circuit implementation
- Patent number 5,991,524
- Issue date Nov 23, 1999
- Cadence Design Systems
- Krishna Belkhale
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Timing model extraction by timing graph reduction
- Publication number 20030121013
- Publication date Jun 26, 2003
- Cadence Design Systems, Inc.
- Cho Woo Moon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Assertion handling for timing model extraction
- Publication number 20030120474
- Publication date Jun 26, 2003
- Cadence Design Systems, Inc.
- Cho Woo Moon
- G06 - COMPUTING CALCULATING COUNTING

Krishna Prasad Belkhale

Person

Patents Grantslast 30 patents

Method, system, and product for deferred merge based method for gra...

Method, system, and product for an improved approach to placement a...

Methods, systems, and articles of manufacture for multi-mode, multi...

System and method for guiding remedial transformations of a circuit...

System and method for common path pessimism reduction in timing ana...

Method and system for implementing an analytical wirelength formula...

Assertion handling for timing model extraction

Method and system for implementing an analytical wirelength formula...

Method and system for implementing an analytical wirelength formula...

Timing model extraction by timing graph reduction

Delay estimation for restructuring

Delay estimation for restructuring the technology independent circuit

Method and apparatus for performing both negative and positive slac...

Cluster matching for circuit implementation

Cluster determination for circuit implementation

Patents Applicationslast 30 patents

Timing model extraction by timing graph reduction

Assertion handling for timing model extraction