Krishna Vijaya Chakravadhanula

Person

Vestal, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Test-point flop sharing with improved testability in a circuit design
- Patent number 11,947,887
- Issue date Apr 2, 2024
- Cadence Design Systems, Inc.
- Krishna Chakravadhanula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method for multiple device diagnostics and failure grouping
- Patent number 10,996,270
- Issue date May 4, 2021
- Cadence Design Systems, Inc.
- Sameer Chillarige
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method to improve testability using 2-dimensional exclusive or (XOR...
- Patent number 10,955,470
- Issue date Mar 23, 2021
- Cadence Design Systems, Inc.
- Brian Edward Foutz
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods for creating learning-based personalized user i...
- Patent number 10,853,100
- Issue date Dec 1, 2020
- Cadence Design Systems, Inc.
- Sonam Kathpalia
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Low-power shift with clock staggering
- Patent number 10,775,435
- Issue date Sep 15, 2020
- Cadence Design Systems, Inc.
- Christos Papameletis
- G01 - MEASURING TESTING
Information Patent Grant
Method for optimally connecting scan segments in two-dimensional co...
- Patent number 10,761,131
- Issue date Sep 1, 2020
- Cadence Design Systems, Inc.
- Christos Papameletis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
2D compression-based low power ATPG
- Patent number 10,551,435
- Issue date Feb 4, 2020
- Cadence Design Systems, Inc.
- Nitin Parimi
- G01 - MEASURING TESTING
Information Patent Grant
Verification process for IJTAG based test pattern migration
- Patent number 10,528,689
- Issue date Jan 7, 2020
- Cadence Design Systems, Inc.
- Rajesh Khurana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
SoC top-level XOR compactor design to efficiently test and diagnose...
- Patent number 10,331,506
- Issue date Jun 25, 2019
- Cadence Design Systems, Inc.
- Vivek Chickermane
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Virtual directory navigation and debugging across multiple test con...
- Patent number 10,325,048
- Issue date Jun 18, 2019
- Cadence Design Systems, Inc.
- Sameer Chakravarthy Chillarige
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for construction of a highly efficient and predic...
- Patent number 9,817,069
- Issue date Nov 14, 2017
- Cadence Design Systems, Inc.
- Steev Wilcox
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for improving efficiency of sequential test compr...
- Patent number 9,817,068
- Issue date Nov 14, 2017
- Cadence Design Systems, Inc.
- Vivek Chickermane
- G01 - MEASURING TESTING
Information Patent Grant
Method and system for improving efficiency of XOR-based test compre...
- Patent number 9,606,179
- Issue date Mar 28, 2017
- Cadence Design Systems, Inc.
- Paul Alexander Cunningham
- G01 - MEASURING TESTING
Information Patent Grant
Method for using XOR trees for physically efficient scan compressio...
- Patent number 9,513,335
- Issue date Dec 6, 2016
- Cadence Design Systems, Inc.
- Steev Wilcox
- G01 - MEASURING TESTING
Information Patent Grant
Method for dividing testable logic into a two-dimensional grid for...
- Patent number 9,470,755
- Issue date Oct 18, 2016
- Cadence Design Systems, Inc.
- Brian Edward Foutz
- G01 - MEASURING TESTING
Information Patent Grant
Elastic compression-optimizing tester bandwidth with compressed tes...
- Patent number 9,470,754
- Issue date Oct 18, 2016
- Cadence Design Systems, Inc.
- Vivek Chickermane
- G01 - MEASURING TESTING
Information Patent Grant
Method for using sequential decompression logic for VLSI test in a...
- Patent number 9,470,756
- Issue date Oct 18, 2016
- Cadence Design Systems, Inc.
- Steev Wilcox
- G01 - MEASURING TESTING
Information Patent Grant
Hierarchical compaction for test pattern power generation
- Patent number 9,170,301
- Issue date Oct 27, 2015
- Cadence Design Systems, Inc.
- Patrick Gallagher
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for low-pin count testing of integrated circuits
- Patent number 8,904,256
- Issue date Dec 2, 2014
- Cadence Design Systems, Inc.
- Krishna Chakravadhanula
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus for low-pin count testing of integrated circuits
- Patent number 8,650,524
- Issue date Feb 11, 2014
- Cadence Design Systems, Inc.
- Krishna Chakravadhanula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for analyzing test vectors to determine toggle co...
- Patent number 8,615,692
- Issue date Dec 24, 2013
- Cadence Design Systems, Inc.
- Rajesh Khurana
- G01 - MEASURING TESTING
Information Patent Grant
Fault modeling for state retention logic
- Patent number 8,296,703
- Issue date Oct 23, 2012
- Cadence Design Systems, Inc.
- Krishna Chakravadhanula
- G11 - INFORMATION STORAGE
Information Patent Grant
System and method for automated synthesis of circuit wrappers
- Patent number 8,296,694
- Issue date Oct 23, 2012
- Cadence Design Systems, Inc.
- Krishna V. Chakravadhanula
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing state retention logic in low power systems
- Patent number 8,271,226
- Issue date Sep 18, 2012
- Cadence Design Systems, Inc.
- Krishna Chakravadhanula
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
METHOD AND SYSTEM FOR PROVIDING EFFICIENT ON-PRODUCT CLOCK GENERATI...
- Publication number 20120124423
- Publication date May 17, 2012
- Cadence Design Systems Inc.
- KRISHNA CHAKRAVADHANULA
- G01 - MEASURING TESTING
Information Patent Application
TESTING STATE RETENTION LOGIC IN LOW POWER SYSTEMS
- Publication number 20090326854
- Publication date Dec 31, 2009
- Cadence Design Systems, Inc.
- Krishna CHAKRAVADHANULA
- G01 - MEASURING TESTING

Krishna Vijaya Chakravadhanula

Person

Patents Grantslast 30 patents

Test-point flop sharing with improved testability in a circuit design

System and method for multiple device diagnostics and failure grouping

Method to improve testability using 2-dimensional exclusive or (XOR...

Systems and methods for creating learning-based personalized user i...

Low-power shift with clock staggering

Method for optimally connecting scan segments in two-dimensional co...

2D compression-based low power ATPG

Verification process for IJTAG based test pattern migration

SoC top-level XOR compactor design to efficiently test and diagnose...

Virtual directory navigation and debugging across multiple test con...

Method and system for construction of a highly efficient and predic...

Method and system for improving efficiency of sequential test compr...

Method and system for improving efficiency of XOR-based test compre...

Method for using XOR trees for physically efficient scan compressio...

Method for dividing testable logic into a two-dimensional grid for...

Elastic compression-optimizing tester bandwidth with compressed tes...

Method for using sequential decompression logic for VLSI test in a...

Hierarchical compaction for test pattern power generation

Method and apparatus for low-pin count testing of integrated circuits

Method and apparatus for low-pin count testing of integrated circuits

Method and system for analyzing test vectors to determine toggle co...

Fault modeling for state retention logic

System and method for automated synthesis of circuit wrappers

Testing state retention logic in low power systems

Patents Applicationslast 30 patents

METHOD AND SYSTEM FOR PROVIDING EFFICIENT ON-PRODUCT CLOCK GENERATI...

TESTING STATE RETENTION LOGIC IN LOW POWER SYSTEMS