KRISHNAN SRINIVASAN

Person

SAN JOSE, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Network-on-chip architecture for handling different data sizes
- Patent number 12,244,518
- Issue date Mar 4, 2025
- Xilinx, Inc.
- Krishnan Srinivasan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
NoC routing in a multi-chip device
- Patent number 12,235,782
- Issue date Feb 25, 2025
- Xilinx, Inc.
- Aman Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
NoC buffer management for virtual channels
- Patent number 12,111,784
- Issue date Oct 8, 2024
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IC with adaptive chip-to-chip interface to support different chip-t...
- Patent number 12,066,969
- Issue date Aug 20, 2024
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamically allocated buffer pooling
- Patent number 12,019,908
- Issue date Jun 25, 2024
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods to transport memory mapped traffic amongst inte...
- Patent number 12,019,576
- Issue date Jun 25, 2024
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed look-ahead routing in network-on-chip
- Patent number 11,985,061
- Issue date May 14, 2024
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive acceleration of transport layer security
- Patent number 11,983,264
- Issue date May 14, 2024
- Xilinx, Inc.
- Jaideep Dastidar
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-use chip-to-chip interface
- Patent number 11,892,966
- Issue date Feb 6, 2024
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for memory management in a video processing sy...
- Patent number 11,887,558
- Issue date Jan 30, 2024
- Xilinx, Inc.
- Krishnan Srinivasan
- G09 - EDUCATION CRYPTOGRAPHY DISPLAY ADVERTISING SEALS
Information Patent Grant
Data bus inversion using multiple transforms
- Patent number 11,755,511
- Issue date Sep 12, 2023
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
On-demand packetization for a chip-to-chip interface
- Patent number 11,636,061
- Issue date Apr 25, 2023
- Xilinx, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system for automatically performing end-to-en...
- Patent number 10,255,399
- Issue date Apr 9, 2019
- Intel Corporation
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method, apparatus and system for automatically deriving parameters...
- Patent number 10,235,486
- Issue date Mar 19, 2019
- Intel Corporation
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System for execution of security related functions
- Patent number 9,208,330
- Issue date Dec 8, 2015
- Avago Technologies General IP (Singapore) Pte. Ltd.
- Krishnan Srinivasan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Apparatus and methods to concurrently perform per-thread as well as...
- Patent number 8,972,995
- Issue date Mar 3, 2015
- Sonics, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quality assessment of text derived from an audio signal
- Patent number 8,892,447
- Issue date Nov 18, 2014
- Nuance Communications, Inc.
- Krishnan Srinivasan
- G10 - MUSICAL INSTRUMENTS ACOUSTICS
Information Patent Grant
Various methods and apparatus for a memory scheduler with an arbiter
- Patent number 8,484,397
- Issue date Jul 9, 2013
- Sonics, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Various methods and apparatus for address tiling and channel interl...
- Patent number 8,438,320
- Issue date May 7, 2013
- Sonics, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and methods for on layer concurrency in an integrated cir...
- Patent number 8,438,306
- Issue date May 7, 2013
- Sonics, Inc.
- Benoit De Lescure
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Performance software instrumentation and analysis for electronic de...
- Patent number 8,229,723
- Issue date Jul 24, 2012
- Sonics, Inc.
- Krishnan Srinivasan
- G01 - MEASURING TESTING
Information Patent Grant
Various methods and apparatus for a memory scheduler with an arbiter
- Patent number 8,190,804
- Issue date May 29, 2012
- Sonics, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Various methods and apparatus for address tiling
- Patent number 8,108,648
- Issue date Jan 31, 2012
- Sonics, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system for a database to monitor and analyze performance...
- Patent number 8,073,820
- Issue date Dec 6, 2011
- Sonics, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
END-TO-END SAFETY MECHANISM FOR DISPLAY SYSTEM
- Publication number 20250080716
- Publication date Mar 6, 2025
- Xilinx, Inc.
- Yanran CHEN
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
INTERCONNECT CIRCUITRY FOR MULTI-CHANNEL AND MULTI-REQUESTER MEMORY...
- Publication number 20250077116
- Publication date Mar 6, 2025
- Xilinx, Inc.
- Ygal ARBEL
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK-ON-CHIP ARCHITECTURE WITH DESTINATION VIRTUALIZATION
- Publication number 20250068583
- Publication date Feb 27, 2025
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM-LEVEL TECHNIQUES FOR ERROR CORRECTION IN CHIP-TO-CHIP INTERF...
- Publication number 20250030500
- Publication date Jan 23, 2025
- Xilinx, Inc.
- Millind MITTAL
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
IIC WITH ADAPTIVE CHIP-TO-CHIP INTERFACE TO SUPPORT DIFFERENT CHIP-...
- Publication number 20240411715
- Publication date Dec 12, 2024
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS TO EXTEND NOC INTERCONNECT ACROSS MULTIPLE DICE IN 3D
- Publication number 20240403253
- Publication date Dec 5, 2024
- Xilinx, Inc.
- Aman GUPTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NOC ROUTING IN A MULTI-CHIP DEVICE
- Publication number 20240211422
- Publication date Jun 27, 2024
- Xilinx, Inc.
- Aman GUPTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOCALIZED AND RELOCATABLE SOFTWARE PLACEMENT AND NOC-BASED ACCESS T...
- Publication number 20240211138
- Publication date Jun 27, 2024
- Xilinx, Inc.
- Aman Gupta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-USE CHIP-TO-CHIP INTERFACE
- Publication number 20240176758
- Publication date May 30, 2024
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-PATH ROUTING IN A NETWORK ON CHIP
- Publication number 20240143891
- Publication date May 2, 2024
- Xilinx, Inc.
- Surya Rajendra Swamy Saranam CHONGALA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT TRANSACTION REDUNDANCY
- Publication number 20240111693
- Publication date Apr 4, 2024
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NOC BUFFER MANAGEMENT FOR VIRTUAL CHANNELS
- Publication number 20240111704
- Publication date Apr 4, 2024
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Systems and Methods to Transport Memory Mapped Traffic amongst inte...
- Publication number 20240045822
- Publication date Feb 8, 2024
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NETWORK-ON-CHIP ARCHITECTURE FOR HANDLING DIFFERENT DATA SIZES
- Publication number 20230370392
- Publication date Nov 16, 2023
- Xilinx, Inc.
- Krishnan Srinivasan
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
ADAPTIVE CHIP-TO-CHIP INTERFACE PROTOCOL ARCHITECTURE
- Publication number 20230244628
- Publication date Aug 3, 2023
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE ACCELERATION OF TRANSPORT LAYER SECURITY
- Publication number 20230177146
- Publication date Jun 8, 2023
- Xilinx, Inc.
- Jaideep DASTIDAR
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-USE CHIP-TO-CHIP INTERFACE
- Publication number 20230141709
- Publication date May 11, 2023
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DATA BUS INVERSION USING MULTIPLE TRANSFORMS
- Publication number 20230069505
- Publication date Mar 2, 2023
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ON-DEMAND PACKETIZATION FOR A CHIP-TO-CHIP INTERFACE
- Publication number 20230066736
- Publication date Mar 2, 2023
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMICALLY ALLOCATED BUFFER POOLING
- Publication number 20230036531
- Publication date Feb 2, 2023
- Xilinx, Inc.
- Krishnan SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method, Apparatus And System For Automatically Performing End-To-En...
- Publication number 20180121574
- Publication date May 3, 2018
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR AUTOMATICALLY DERIVING PARAMETERS...
- Publication number 20180089342
- Publication date Mar 29, 2018
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM FOR EXECUTION OF SECURITY RELATED FUNCTIONS
- Publication number 20150220744
- Publication date Aug 6, 2015
- LSI Corporation
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS FOR ON LAYER CONCURRENCY IN AN INTEGRATED CIR...
- Publication number 20120110106
- Publication date May 3, 2012
- Sonics, Inc.
- BENOIT DE LESCURE
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHODS TO CONCURRENTLY PERFORM PER-THREAD AS WELL AS...
- Publication number 20120036509
- Publication date Feb 9, 2012
- Sonics, Inc.
- KRISHNAN SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIOUS METHODS AND APPARATUS FOR ADDRESS TILING AND CHANNEL INTERL...
- Publication number 20100042759
- Publication date Feb 18, 2010
- Sonics, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND SYSTEM FOR A DATABASE TO MONITOR AND ANALYZE PERFORMANCE...
- Publication number 20090254525
- Publication date Oct 8, 2009
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIOUS METHODS AND APPARATUS FOR ADDRESS TILING
- Publication number 20090235020
- Publication date Sep 17, 2009
- Sonics, Inc.
- Krishnan Srinivasan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PERFORMANCE SOFTWARE INSTRUMENTATION AND ANALYSIS FOR ELECTRONIC DE...
- Publication number 20090150857
- Publication date Jun 11, 2009
- KRISHNAN SRINIVASAN
- G06 - COMPUTING CALCULATING COUNTING

KRISHNAN SRINIVASAN

Person

Patents Grantslast 30 patents

Network-on-chip architecture for handling different data sizes

NoC routing in a multi-chip device

NoC buffer management for virtual channels

IC with adaptive chip-to-chip interface to support different chip-t...

Dynamically allocated buffer pooling

Systems and methods to transport memory mapped traffic amongst inte...

Distributed look-ahead routing in network-on-chip

Adaptive acceleration of transport layer security

Multi-use chip-to-chip interface

Method and apparatus for memory management in a video processing sy...

Data bus inversion using multiple transforms

On-demand packetization for a chip-to-chip interface

Method, apparatus and system for automatically performing end-to-en...

Method, apparatus and system for automatically deriving parameters...

System for execution of security related functions

Apparatus and methods to concurrently perform per-thread as well as...

Quality assessment of text derived from an audio signal

Various methods and apparatus for a memory scheduler with an arbiter

Various methods and apparatus for address tiling and channel interl...

Apparatus and methods for on layer concurrency in an integrated cir...

Performance software instrumentation and analysis for electronic de...

Various methods and apparatus for a memory scheduler with an arbiter

Various methods and apparatus for address tiling

Method and system for a database to monitor and analyze performance...

Patents Applicationslast 30 patents

END-TO-END SAFETY MECHANISM FOR DISPLAY SYSTEM

INTERCONNECT CIRCUITRY FOR MULTI-CHANNEL AND MULTI-REQUESTER MEMORY...

NETWORK-ON-CHIP ARCHITECTURE WITH DESTINATION VIRTUALIZATION

SYSTEM-LEVEL TECHNIQUES FOR ERROR CORRECTION IN CHIP-TO-CHIP INTERF...

IIC WITH ADAPTIVE CHIP-TO-CHIP INTERFACE TO SUPPORT DIFFERENT CHIP-...

METHODS TO EXTEND NOC INTERCONNECT ACROSS MULTIPLE DICE IN 3D

NOC ROUTING IN A MULTI-CHIP DEVICE

LOCALIZED AND RELOCATABLE SOFTWARE PLACEMENT AND NOC-BASED ACCESS T...

MULTI-USE CHIP-TO-CHIP INTERFACE

MULTI-PATH ROUTING IN A NETWORK ON CHIP

INTEGRATED CIRCUIT TRANSACTION REDUNDANCY

NOC BUFFER MANAGEMENT FOR VIRTUAL CHANNELS

Systems and Methods to Transport Memory Mapped Traffic amongst inte...

NETWORK-ON-CHIP ARCHITECTURE FOR HANDLING DIFFERENT DATA SIZES

ADAPTIVE CHIP-TO-CHIP INTERFACE PROTOCOL ARCHITECTURE

ADAPTIVE ACCELERATION OF TRANSPORT LAYER SECURITY

MULTI-USE CHIP-TO-CHIP INTERFACE

DATA BUS INVERSION USING MULTIPLE TRANSFORMS

ON-DEMAND PACKETIZATION FOR A CHIP-TO-CHIP INTERFACE

DYNAMICALLY ALLOCATED BUFFER POOLING

Method, Apparatus And System For Automatically Performing End-To-En...

METHOD, APPARATUS AND SYSTEM FOR AUTOMATICALLY DERIVING PARAMETERS...

SYSTEM FOR EXECUTION OF SECURITY RELATED FUNCTIONS

APPARATUS AND METHODS FOR ON LAYER CONCURRENCY IN AN INTEGRATED CIR...

APPARATUS AND METHODS TO CONCURRENTLY PERFORM PER-THREAD AS WELL AS...

VARIOUS METHODS AND APPARATUS FOR ADDRESS TILING AND CHANNEL INTERL...

METHOD AND SYSTEM FOR A DATABASE TO MONITOR AND ANALYZE PERFORMANCE...

VARIOUS METHODS AND APPARATUS FOR ADDRESS TILING

PERFORMANCE SOFTWARE INSTRUMENTATION AND ANALYSIS FOR ELECTRONIC DE...