Krishnendu Chakrabarty

Person

Chapel Hill, NC, US

People

Patents Grantslast 30 patents

Information Patent Grant
Dynamic scan obfuscation for integrated circuit protections
- Patent number 12,072,379
- Issue date Aug 27, 2024
- Duke University
- Krishnendu Chakrabarty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Evaluating functional fault criticality of structural faults for ci...
- Patent number 12,008,298
- Issue date Jun 11, 2024
- Duke University
- Krishnendu Chakrabarty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Online fault detection in ReRAM-based AI/ML
- Patent number 11,971,790
- Issue date Apr 30, 2024
- NVIDIA Corporation
- Krishnendu Chakrabarty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Observation point injection for integrated circuit testing
- Patent number 11,714,129
- Issue date Aug 1, 2023
- Duke University
- Krishnendu Chakrabarty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Variation-aware delay fault testing
- Patent number 11,568,113
- Issue date Jan 31, 2023
- Duke University
- Krishnendu Chakrabarty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Software-based self-test and diagnosis using on-chip memory
- Patent number 10,845,416
- Issue date Nov 24, 2020
- Duke University
- Sergej Deutsch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Multi-layer integrated circuits having isolation cells for layer te...
- Patent number 10,838,003
- Issue date Nov 17, 2020
- Duke University
- Krishnendu Chakrabarty
- G01 - MEASURING TESTING
Information Patent Grant
Software-based self-test and diagnosis using on-chip memory
- Patent number 10,788,532
- Issue date Sep 29, 2020
- Duke University
- Sergej Deutsch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Testing monolithic three dimensional integrated circuits
- Patent number 10,775,429
- Issue date Sep 15, 2020
- Marvell Asia Pte., Ltd.
- Sukeshwar Kannan
- G01 - MEASURING TESTING
Information Patent Grant
Signal tracing using on-chip memory for in-system post-fabrication...
- Patent number 10,732,221
- Issue date Aug 4, 2020
- Duke University
- Sergej Deutsch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-invasive pre-bond TSV test using ring oscillators and multiple...
- Patent number 10,444,279
- Issue date Oct 15, 2019
- Duke University
- Krishnendu Chakrabarty
- G01 - MEASURING TESTING
Information Patent Grant
Multi-layer integrated circuits having isolation cells for layer te...
- Patent number 10,338,133
- Issue date Jul 2, 2019
- Duke University
- Krishnendu Chakrabarty
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Software-based self-test and diagnosis using on-chip memory
- Patent number 9,864,007
- Issue date Jan 9, 2018
- Duke University
- Sergej Deutsch
- G11 - INFORMATION STORAGE
Information Patent Grant
Signal tracing using on-chip memory for in-system post-fabrication...
- Patent number 9,720,036
- Issue date Aug 1, 2017
- Duke University
- Sergej Deutsch
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Non-invasive pre-bond TSV test using ring oscillators and multiple...
- Patent number 9,482,720
- Issue date Nov 1, 2016
- Duke University
- Krishnendu Chakrabarty
- G01 - MEASURING TESTING
Information Patent Grant
Print production scheduling
- Patent number 9,367,268
- Issue date Jun 14, 2016
- Hewlett-Packard Development Company, L.P.
- Jun Zeng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Architectural layout for dilution with reduced wastage in digital m...
- Patent number 9,201,042
- Issue date Dec 1, 2015
- Indian Statistical Institute
- Bhargab B. Bhattacharya
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Grant
High throughput and volumetric error resilient dilution with digita...
- Patent number 9,128,014
- Issue date Sep 8, 2015
- Indian Statistical Institute
- Bhargab B. Bhattacharya
- G01 - MEASURING TESTING
Information Patent Grant
Retiming-based design flow for delay recovery on inter-die paths in...
- Patent number 8,832,608
- Issue date Sep 9, 2014
- Duke University
- Krishnendu Chakrabarty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Scan test of die logic in 3D ICs using TSV probing
- Patent number 8,782,479
- Issue date Jul 15, 2014
- Duke University
- Krishnendu Chakrabarty
- G01 - MEASURING TESTING
Information Patent Grant
Method and architecture for pre-bond probing of TSVs in 3D stacked...
- Patent number 8,775,108
- Issue date Jul 8, 2014
- Duke University
- Krishnendu Chakrabarty
- G01 - MEASURING TESTING
Information Patent Grant
Power switch design and method for reducing leakage power in low-po...
- Patent number 8,373,493
- Issue date Feb 12, 2013
- Duke University
- Krishnendu Chakrabarty
- H03 - BASIC ELECTRONIC CIRCUITRY

Patents Applicationslast 30 patents

Information Patent Application
ONLINE FAULT DETECTION IN RERAM-BASED AI/ML
- Publication number 20240289239
- Publication date Aug 29, 2024
- NVIDIA Corporation
- Krishnendu Chakrabarty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC SCAN OBFUSCATION FOR INTEGRATED CIRCUIT PROTECTIONS
- Publication number 20230288477
- Publication date Sep 14, 2023
- DUKE UNIVERSITY
- Krishnendu CHAKRABARTY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAULT CRITICALITY ASSESSMENT USING NEURAL TWINS
- Publication number 20230108103
- Publication date Apr 6, 2023
- DUKE UNIVERSITY
- Krishnendu Chakrabarty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FAULT CRITICALITY ASSESSMENT USING GRAPH CONVOLUTIONAL NETWORKS
- Publication number 20220245439
- Publication date Aug 4, 2022
- DUKE UNIVERSITY
- Krishnendu CHAKRABARTY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EVALUATING FUNCTIONAL FAULT CRITICALITY OF STRUCTURAL FAULTS FOR CI...
- Publication number 20220129732
- Publication date Apr 28, 2022
- DUKE UNIVERSITY
- Krishnendu CHAKRABARTY
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VARIATION-AWARE DELAY FAULT TESTING
- Publication number 20220067250
- Publication date Mar 3, 2022
- DUKE UNIVERSITY
- Krishnendu Chakrabarty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ONLINE FAULT DETECTION IN RERAM-BASED AI/ML
- Publication number 20220066888
- Publication date Mar 3, 2022
- NVIDIA Corporation
- Krishnendu Chakrabarty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OBSERVATION POINT INJECTION FOR INTEGRATED CIRCUIT TESTING
- Publication number 20220065926
- Publication date Mar 3, 2022
- DUKE UNIVERSITY
- Krishnendu Chakrabarty
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT IDENTIFICATION OF CRITICAL FAULTS IN NEUROMORPHIC HARDWAR...
- Publication number 20220067531
- Publication date Mar 3, 2022
- NVIDIA Corporation
- Ching-Yuan Chen
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI-LAYER INTEGRATED CIRCUITS HAVING ISOLATION CELLS FOR LAYER TE...
- Publication number 20190302179
- Publication date Oct 3, 2019
- DUKE UNIVERSITY
- Krishnendu Chakrabarty
- G01 - MEASURING TESTING
Information Patent Application
TESTING MONOLITHIC THREE DIMENSIONAL INTEGRATED CIRCUITS
- Publication number 20190094294
- Publication date Mar 28, 2019
- DUKE UNIVERSITY
- Sukeshwar Kannan
- G01 - MEASURING TESTING
Information Patent Application
SOFTWARE-BASED SELF-TEST AND DIAGNOSIS USING ON-CHIP MEMORY
- Publication number 20180095128
- Publication date Apr 5, 2018
- DUKE UNIVERSITY
- SERGEJ DEUTSCH
- G01 - MEASURING TESTING
Information Patent Application
SOFTWARE-BASED SELF-TEST AND DIAGNOSIS USING ON-CHIP MEMORY
- Publication number 20180095129
- Publication date Apr 5, 2018
- DUKE UNIVERSITY
- SERGEJ DEUTSCH
- G01 - MEASURING TESTING
Information Patent Application
MULTI-LAYER INTEGRATED CIRCUITS HAVING ISOLATION CELLS FOR LAYER TE...
- Publication number 20170343603
- Publication date Nov 30, 2017
- DUKE UNIVERSITY
- Krishnendu Chakrabarty
- G01 - MEASURING TESTING
Information Patent Application
SIGNAL TRACING USING ON-CHIP MEMORY FOR IN-SYSTEM POST-FABRICATION...
- Publication number 20170299655
- Publication date Oct 19, 2017
- DUKE UNIVERSITY
- SERGEJ DEUTSCH
- G01 - MEASURING TESTING
Information Patent Application
NON-INVASIVE PRE-BOND TSV USING RING OSCILLATORS AND MULTIPLE VOLTA...
- Publication number 20170003340
- Publication date Jan 5, 2017
- DUKE UNIVERSITY
- KRISHNENDU CHAKRABARTY
- G01 - MEASURING TESTING
Information Patent Application
SIGNAL TRACING USING ON-CHIP MEMORY FOR IN-SYSTEM POST-FABRICATION...
- Publication number 20160047859
- Publication date Feb 18, 2016
- DUKE UNIVERSITY
- SERGEJ DEUTSCH
- G01 - MEASURING TESTING
Information Patent Application
SOFTWARE-BASED SELF-TEST AND DIAGNOSIS USING ON-CHIP MEMORY
- Publication number 20150316605
- Publication date Nov 5, 2015
- DUKE UNIVERSITY
- SERGEJ DEUTSCH
- G01 - MEASURING TESTING
Information Patent Application
Print Production Scheduling
- Publication number 20150098110
- Publication date Apr 9, 2015
- Jun Zeng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
NON-INVASIVE PRE-BOND TSV TEST USING RING OSCILLATORS AND MULTIPLE...
- Publication number 20140225624
- Publication date Aug 14, 2014
- DUKE UNIVERSITY
- KRISHNENDU CHAKRABARTY
- G01 - MEASURING TESTING
Information Patent Application
Validating Feasibility of Proposed Contract Provisions
- Publication number 20140136268
- Publication date May 15, 2014
- Hewlett-Packard Development Company, L.P.
- Jun Zeng
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN TEST OF DIE LOGIC IN 3D ICs USING TSV PROBING
- Publication number 20140122951
- Publication date May 1, 2014
- DUKE UNIVERSITY
- Krishnendu Chakrabarty
- G01 - MEASURING TESTING
Information Patent Application
DILUTION METHOD FOR DIGITAL MICROFLUIDIC BIOCHIPS
- Publication number 20130115703
- Publication date May 9, 2013
- INDIAN STATISTICAL INSTITUTE
- Bhargab B. Bhattacharya
- G01 - MEASURING TESTING
Information Patent Application
HIGH THROUGHPUT AND VOLUMETRIC ERROR RESILIENT DILUTION WITH DIGITA...
- Publication number 20130105318
- Publication date May 2, 2013
- Indian Statistical Institute
- Bhargab B. Bhattacharya
- G01 - MEASURING TESTING
Information Patent Application
ARCHITECTURAL LAYOUT FOR DILUTION WITH REDUCED WASTAGE IN DIGITAL M...
- Publication number 20130105319
- Publication date May 2, 2013
- INDIAN STATISTICAL INSTITUTE
- Bhargab B. Bhattacharya
- B81 - MICRO-STRUCTURAL TECHNOLOGY
Information Patent Application
METHOD AND ARCHITECTURE FOR PRE-BOND PROBING OF TSVs IN 3D STACKED...
- Publication number 20130006557
- Publication date Jan 3, 2013
- DUKE UNIVERSITY
- Krishnendu Chakrabarty
- G01 - MEASURING TESTING
Information Patent Application
POWER SWITCH DESIGN AND METHOD FOR REDUCING LEAKAGE POWER IN LOW-PO...
- Publication number 20120062308
- Publication date Mar 15, 2012
- KRISHNENDU CHAKRABARTY
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Droplet Actuators, Systems and Methods
- Publication number 20100236929
- Publication date Sep 23, 2010
- ADVANCED LIQUID LOGIC, INC.
- Michael G. Pollack
- B01 - PHYSICAL OR CHEMICAL PROCESSES OR APPARATUS IN GENERAL
Information Patent Application
Self-organizing sensor node network
- Publication number 20060253570
- Publication date Nov 9, 2006
- Pratik Biswas
- H04 - ELECTRIC COMMUNICATION TECHNIQUE

Krishnendu Chakrabarty

Person

Patents Grantslast 30 patents

Dynamic scan obfuscation for integrated circuit protections

Evaluating functional fault criticality of structural faults for ci...

Online fault detection in ReRAM-based AI/ML

Observation point injection for integrated circuit testing

Variation-aware delay fault testing

Software-based self-test and diagnosis using on-chip memory

Multi-layer integrated circuits having isolation cells for layer te...

Software-based self-test and diagnosis using on-chip memory

Testing monolithic three dimensional integrated circuits

Signal tracing using on-chip memory for in-system post-fabrication...

Non-invasive pre-bond TSV test using ring oscillators and multiple...

Multi-layer integrated circuits having isolation cells for layer te...

Software-based self-test and diagnosis using on-chip memory

Signal tracing using on-chip memory for in-system post-fabrication...

Non-invasive pre-bond TSV test using ring oscillators and multiple...

Print production scheduling

Architectural layout for dilution with reduced wastage in digital m...

High throughput and volumetric error resilient dilution with digita...

Retiming-based design flow for delay recovery on inter-die paths in...

Scan test of die logic in 3D ICs using TSV probing

Method and architecture for pre-bond probing of TSVs in 3D stacked...

Power switch design and method for reducing leakage power in low-po...

Patents Applicationslast 30 patents

ONLINE FAULT DETECTION IN RERAM-BASED AI/ML

DYNAMIC SCAN OBFUSCATION FOR INTEGRATED CIRCUIT PROTECTIONS

FAULT CRITICALITY ASSESSMENT USING NEURAL TWINS

FAULT CRITICALITY ASSESSMENT USING GRAPH CONVOLUTIONAL NETWORKS

EVALUATING FUNCTIONAL FAULT CRITICALITY OF STRUCTURAL FAULTS FOR CI...

VARIATION-AWARE DELAY FAULT TESTING

ONLINE FAULT DETECTION IN RERAM-BASED AI/ML

OBSERVATION POINT INJECTION FOR INTEGRATED CIRCUIT TESTING

EFFICIENT IDENTIFICATION OF CRITICAL FAULTS IN NEUROMORPHIC HARDWAR...

MULTI-LAYER INTEGRATED CIRCUITS HAVING ISOLATION CELLS FOR LAYER TE...

TESTING MONOLITHIC THREE DIMENSIONAL INTEGRATED CIRCUITS

SOFTWARE-BASED SELF-TEST AND DIAGNOSIS USING ON-CHIP MEMORY

SOFTWARE-BASED SELF-TEST AND DIAGNOSIS USING ON-CHIP MEMORY

MULTI-LAYER INTEGRATED CIRCUITS HAVING ISOLATION CELLS FOR LAYER TE...

SIGNAL TRACING USING ON-CHIP MEMORY FOR IN-SYSTEM POST-FABRICATION...

NON-INVASIVE PRE-BOND TSV USING RING OSCILLATORS AND MULTIPLE VOLTA...

SIGNAL TRACING USING ON-CHIP MEMORY FOR IN-SYSTEM POST-FABRICATION...

SOFTWARE-BASED SELF-TEST AND DIAGNOSIS USING ON-CHIP MEMORY

Print Production Scheduling

NON-INVASIVE PRE-BOND TSV TEST USING RING OSCILLATORS AND MULTIPLE...

Validating Feasibility of Proposed Contract Provisions

SCAN TEST OF DIE LOGIC IN 3D ICs USING TSV PROBING

DILUTION METHOD FOR DIGITAL MICROFLUIDIC BIOCHIPS

HIGH THROUGHPUT AND VOLUMETRIC ERROR RESILIENT DILUTION WITH DIGITA...

ARCHITECTURAL LAYOUT FOR DILUTION WITH REDUCED WASTAGE IN DIGITAL M...

METHOD AND ARCHITECTURE FOR PRE-BOND PROBING OF TSVs IN 3D STACKED...

POWER SWITCH DESIGN AND METHOD FOR REDUCING LEAKAGE POWER IN LOW-PO...

Droplet Actuators, Systems and Methods

Self-organizing sensor node network