Krste Asanovic

Person

Berkeley, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Memory protection for gather-scatter operations
- Patent number 12,253,959
- Issue date Mar 18, 2025
- SiFive, Inc.
- Andrew Waterman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Load-store pipeline selection for vectors
- Patent number 12,086,067
- Issue date Sep 10, 2024
- SiFive, Inc.
- Andrew Waterman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Checker cores for fault tolerant processing
- Patent number 11,966,290
- Issue date Apr 23, 2024
- SiFive, Inc.
- Murali Vijayaraghavan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Macro-op fusion
- Patent number 11,861,365
- Issue date Jan 2, 2024
- SiFive, Inc.
- Krste Asanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fetch stage handling of indirect jumps in a processor pipeline
- Patent number 11,797,308
- Issue date Oct 24, 2023
- SiFive, Inc.
- Joshua Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Way predictor and enable logic for instruction tightly-coupled memo...
- Patent number 11,687,342
- Issue date Jun 27, 2023
- SiFive, Inc.
- Krste Asanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Checker cores for fault tolerant processing
- Patent number 11,556,413
- Issue date Jan 17, 2023
- SiFive, Inc.
- Murali Vijayaraghavan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure predictors for speculative execution
- Patent number 11,429,392
- Issue date Aug 30, 2022
- SiFive, Inc.
- Krste Asanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Secure control flow prediction
- Patent number 11,347,507
- Issue date May 31, 2022
- SiFive, Inc.
- Alex Solomatnikov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Fetch stage handling of indirect jumps in a processor pipeline
- Patent number 11,301,251
- Issue date Apr 12, 2022
- SiFive, Inc.
- Joshua Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Way predictor and enable logic for instruction tightly-coupled memo...
- Patent number 11,048,515
- Issue date Jun 29, 2021
- SiFive, Inc.
- Krste Asanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Macro-op fusion
- Patent number 10,996,952
- Issue date May 4, 2021
- SiFive, Inc.
- Krste Asanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Vector processing system with multi-operation, run-time configurabl...
- Patent number 5,805,875
- Issue date Sep 8, 1998
- International Computer Science Institute
- Krste Asanovic
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PAGE TABLE ENTRY CACHES WITH MULTIPLE TAG LENGTHS
- Publication number 20240338320
- Publication date Oct 10, 2024
- SiFive, Inc.
- Perrine Peresse
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Error Management In System On A Chip With Securely Partitioned Memo...
- Publication number 20240303205
- Publication date Sep 12, 2024
- SiFive, Inc.
- Krste Asanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Address Range Encoding in System on a Chip with Securely Partitione...
- Publication number 20240289495
- Publication date Aug 29, 2024
- SiFive, Inc.
- Krste Asanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Macro-Op Fusion for Pipelined Architectures
- Publication number 20240264839
- Publication date Aug 8, 2024
- SiFive, Inc.
- Andrew Waterman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURABLE INTERCONNECT ADDRESS REMAPPER WITH EVENT RECOGNITION
- Publication number 20240160449
- Publication date May 16, 2024
- SiFive, Inc.
- David Parry
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Supporting Multiple Vector Lengths with Configurable Vector Registe...
- Publication number 20240020124
- Publication date Jan 18, 2024
- SiFive, Inc.
- Andrew Waterman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fusion with Destructive Instructions
- Publication number 20240020126
- Publication date Jan 18, 2024
- SiFive, Inc.
- Andrew Waterman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
EFFICIENT PROCESSING OF MASKED MEMORY ACCESSES
- Publication number 20240012948
- Publication date Jan 11, 2024
- SiFive, Inc.
- Andrew Waterman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Vector Gather with a Narrow Datapath
- Publication number 20230367599
- Publication date Nov 16, 2023
- SiFive, Inc.
- Andrew Waterman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Load-Store Pipeline Selection For Vectors
- Publication number 20230367715
- Publication date Nov 16, 2023
- SiFive, Inc.
- Andrew Waterman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CONFIGURING A COMPONENT OF A PROCESSOR CORE BASED ON AN ATTRIBUTE O...
- Publication number 20230333861
- Publication date Oct 19, 2023
- SiFive, Inc.
- Krste Asanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY PROTECTION FOR VECTOR OPERATIONS
- Publication number 20230315649
- Publication date Oct 5, 2023
- SiFive, Inc.
- Krste Asanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEMORY PROTECTION FOR GATHER-SCATTER OPERATIONS
- Publication number 20230305969
- Publication date Sep 28, 2023
- SiFive, Inc.
- Andrew Waterman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REGISTER RENAMING FOR POWER CONSERVATION
- Publication number 20230305852
- Publication date Sep 28, 2023
- SiFive, Inc.
- Krste Asanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Checker Cores for Fault Tolerant Processing
- Publication number 20230153203
- Publication date May 18, 2023
- SiFive, Inc.
- Murali Vijayaraghavan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURE CONTROL FLOW PREDICTION
- Publication number 20220292183
- Publication date Sep 15, 2022
- SiFive, Inc.
- Alex Solomatnikov
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FETCH STAGE HANDLING OF INDIRECT JUMPS IN A PROCESSOR PIPELINE
- Publication number 20220236993
- Publication date Jul 28, 2022
- SiFive, Inc.
- Joshua Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAY PREDICTOR AND ENABLE LOGIC FOR INSTRUCTION TIGHTLY-COUPLED MEMO...
- Publication number 20220083340
- Publication date Mar 17, 2022
- SiFive, Inc.
- Krste Asanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FETCH STAGE HANDLING OF INDIRECT JUMPS IN A PROCESSOR PIPELINE
- Publication number 20210303300
- Publication date Sep 30, 2021
- SiFive, Inc.
- Joshua Smith
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACRO-OP FUSION
- Publication number 20210255859
- Publication date Aug 19, 2021
- SiFive, Inc.
- Krste Asanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Checker Cores for Fault Tolerant Processing
- Publication number 20210173738
- Publication date Jun 10, 2021
- SiFive, Inc.
- Murali Vijayaraghavan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION TIGHTLY-COUPLED MEMORY AND INSTRUCTION CACHE ACCESS PRE...
- Publication number 20200210189
- Publication date Jul 2, 2020
- SiFive, Inc.
- Krste Asanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURE PREDICTORS FOR SPECULATIVE EXECUTION
- Publication number 20200210197
- Publication date Jul 2, 2020
- SiFive, Inc.
- Krste Asanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MACRO-OP FUSION
- Publication number 20200183687
- Publication date Jun 11, 2020
- SiFive, Inc.
- Krste Asanovic
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SECURE CONTROL FLOW PREDICTION
- Publication number 20190286443
- Publication date Sep 19, 2019
- SiFive, Inc.
- Alex Solomatnikov
- G06 - COMPUTING CALCULATING COUNTING

Krste Asanovic

Person

Patents Grantslast 30 patents

Memory protection for gather-scatter operations

Load-store pipeline selection for vectors

Checker cores for fault tolerant processing

Macro-op fusion

Fetch stage handling of indirect jumps in a processor pipeline

Way predictor and enable logic for instruction tightly-coupled memo...

Checker cores for fault tolerant processing

Secure predictors for speculative execution

Secure control flow prediction

Fetch stage handling of indirect jumps in a processor pipeline

Way predictor and enable logic for instruction tightly-coupled memo...

Macro-op fusion

Vector processing system with multi-operation, run-time configurabl...

Patents Applicationslast 30 patents

PAGE TABLE ENTRY CACHES WITH MULTIPLE TAG LENGTHS

Error Management In System On A Chip With Securely Partitioned Memo...

Address Range Encoding in System on a Chip with Securely Partitione...

Macro-Op Fusion for Pipelined Architectures

CONFIGURABLE INTERCONNECT ADDRESS REMAPPER WITH EVENT RECOGNITION

Supporting Multiple Vector Lengths with Configurable Vector Registe...

Fusion with Destructive Instructions

EFFICIENT PROCESSING OF MASKED MEMORY ACCESSES

Vector Gather with a Narrow Datapath

Load-Store Pipeline Selection For Vectors

CONFIGURING A COMPONENT OF A PROCESSOR CORE BASED ON AN ATTRIBUTE O...

MEMORY PROTECTION FOR VECTOR OPERATIONS

MEMORY PROTECTION FOR GATHER-SCATTER OPERATIONS

REGISTER RENAMING FOR POWER CONSERVATION

Checker Cores for Fault Tolerant Processing

SECURE CONTROL FLOW PREDICTION

FETCH STAGE HANDLING OF INDIRECT JUMPS IN A PROCESSOR PIPELINE

WAY PREDICTOR AND ENABLE LOGIC FOR INSTRUCTION TIGHTLY-COUPLED MEMO...

FETCH STAGE HANDLING OF INDIRECT JUMPS IN A PROCESSOR PIPELINE

MACRO-OP FUSION

Checker Cores for Fault Tolerant Processing

INSTRUCTION TIGHTLY-COUPLED MEMORY AND INSTRUCTION CACHE ACCESS PRE...

SECURE PREDICTORS FOR SPECULATIVE EXECUTION

MACRO-OP FUSION

SECURE CONTROL FLOW PREDICTION