Kuei-Chun Hung

Person

Hsinchu City, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit
- Patent number 11,482,517
- Issue date Oct 25, 2022
- United Microelectronics Corp.
- En-Chiuan Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor integrated circuit layout structure
- Patent number 9,905,562
- Issue date Feb 27, 2018
- United Microelectronics Corp.
- Shih-Chin Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor integrated circuit layout structure
- Patent number 9,673,145
- Issue date Jun 6, 2017
- United Microelectronics Corp.
- Shih-Chin Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated FinFET structure having a contact plug pitch larger than...
- Patent number 9,653,346
- Issue date May 16, 2017
- United Microelectronics Corp.
- Shih-Chin Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of decomposing layout for generating patterns on photomasks
- Patent number 9,524,362
- Issue date Dec 20, 2016
- United Microelectronics Corp.
- Harn-Jiunn Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Measurement method of overlay mark
- Patent number 9,007,571
- Issue date Apr 14, 2015
- United Microelectronics Corp.
- Wei-Jhe Tzai
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method for forming a plane structure
- Patent number 7,101,796
- Issue date Sep 5, 2006
- United Microelectronics Corp.
- Jui-Tsen Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Photolithography process with multiple exposures
- Patent number 6,839,126
- Issue date Jan 4, 2005
- United Microelectronics Corp.
- Yeong-Song Yen
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Optical mask correction method
- Patent number 6,638,664
- Issue date Oct 28, 2003
- United Microelectronics Corp.
- Chang-Jyh Hsieh
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Method for forming a plane structure
- Patent number 6,624,055
- Issue date Sep 23, 2003
- United Microelectronics Corp.
- Jui-Tsen Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming dual damascene structure
- Patent number 6,589,881
- Issue date Jul 8, 2003
- United Microelectronics Corp.
- I-Hsiung Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for forming via-first dual damascene interconnect structure
- Patent number 6,458,705
- Issue date Oct 1, 2002
- United Microelectronics Corp.
- Kuei-Chun Hung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating a dual damascene structure
- Patent number 6,337,269
- Issue date Jan 8, 2002
- United Microelectronics Corp.
- I-Hsiung Huang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT
- Publication number 20180261589
- Publication date Sep 13, 2018
- UNITED MICROELECTRONICS CORP.
- En-Chiuan Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT LAYOUT STRUCTURE
- Publication number 20170221897
- Publication date Aug 3, 2017
- UNITED MICROELECTRONICS CORP.
- Shih-Chin LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT AND PROCESS THEREOF
- Publication number 20170117151
- Publication date Apr 27, 2017
- UNITED MICROELECTRONICS CORP.
- En-Chiuan Liou
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR FORMING THE SAME
- Publication number 20160329241
- Publication date Nov 10, 2016
- UNITED MICROELECTRONICS CORP.
- Shih-Chin LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR INTEGRATED CIRCUIT LAYOUT STRUCTURE
- Publication number 20160329276
- Publication date Nov 10, 2016
- UNITED MICROELECTRONICS CORP.
- Shih-Chin LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF DECOMPOSING LAYOUT FOR GENERATING PATTERNS ON PHOTOMASKS
- Publication number 20160314233
- Publication date Oct 27, 2016
- UNITED MICROELECTRONICS CORP.
- Harn-Jiunn Wang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MEASUREMENT MARK STRUCTURE
- Publication number 20150276382
- Publication date Oct 1, 2015
- UNITED MICROELECTRONICS CORP.
- En-Chiuan Liou
- G01 - MEASURING TESTING
Information Patent Application
MEASUREMENT METHOD OF OVERLAY MARK
- Publication number 20150055125
- Publication date Feb 26, 2015
- United Microelectronics Corp.
- Wei-Jhe Tzai
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
Method for forming a plane structure
- Publication number 20050277301
- Publication date Dec 15, 2005
- UNITED MICROELECTRONICS CORP.
- Jui-Tsen Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for forming a plane structure
- Publication number 20040033628
- Publication date Feb 19, 2004
- United Microelectronics Corp.
- Jui-Tsen Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Photolithography process with multiple exposures
- Publication number 20030123039
- Publication date Jul 3, 2003
- Yeong-Song Yen
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
METHOD OF FORMING DUAL DAMASCENE STRUCTURE
- Publication number 20030100188
- Publication date May 29, 2003
- I-Hsiung Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of forming dual damascene structure
- Publication number 20030096496
- Publication date May 22, 2003
- I-Hsiung Huang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Optical mask correction method
- Publication number 20020182550
- Publication date Dec 5, 2002
- Chang-Jyh Hsieh
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY

Kuei-Chun Hung

Person

Patents Grantslast 30 patents

Integrated circuit

Semiconductor integrated circuit layout structure

Semiconductor integrated circuit layout structure

Integrated FinFET structure having a contact plug pitch larger than...

Method of decomposing layout for generating patterns on photomasks

Measurement method of overlay mark

Method for forming a plane structure

Photolithography process with multiple exposures

Optical mask correction method

Method for forming a plane structure

Method of forming dual damascene structure

Method for forming via-first dual damascene interconnect structure

Method of fabricating a dual damascene structure

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT

SEMICONDUCTOR INTEGRATED CIRCUIT LAYOUT STRUCTURE

INTEGRATED CIRCUIT AND PROCESS THEREOF

INTEGRATED CIRCUIT STRUCTURE AND METHOD FOR FORMING THE SAME

SEMICONDUCTOR INTEGRATED CIRCUIT LAYOUT STRUCTURE

METHOD OF DECOMPOSING LAYOUT FOR GENERATING PATTERNS ON PHOTOMASKS

MEASUREMENT MARK STRUCTURE

MEASUREMENT METHOD OF OVERLAY MARK

Method for forming a plane structure

Method for forming a plane structure

Photolithography process with multiple exposures

METHOD OF FORMING DUAL DAMASCENE STRUCTURE

Method of forming dual damascene structure

Optical mask correction method