Kuen-Chy Heo

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Chiai Hsien, TW

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Patents Grantslast 30 patents

Information Patent Grant
Layout of a folded bitline DRAM with a borderless bitline
- Patent number 6,781,181
- Issue date Aug 24, 2004
- Nanya Technology Corporation
- Kuen-Chy Heo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating memory cell
- Patent number 6,534,359
- Issue date Mar 18, 2003
- Nanya Technology Corporation
- Kuen-Chy Heo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating memory cell with trench capacitor and vertica...
- Patent number 6,432,774
- Issue date Aug 13, 2002
- Nanya Technology Corporation
- Kuen-Chy Heo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of fabricating memory cell with vertical transistor
- Patent number 6,355,529
- Issue date Mar 12, 2002
- Nanya Technology Corporation
- Kuen-Chy Heo
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
DRAM with vertical transistors and deep trench capacitors
- Publication number 20030201481
- Publication date Oct 30, 2003
- NANYA TECHNOLOGY CORPORATION
- Kuen-Chy Heo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DRAM with vertical transistors and deep trench capacitors
- Publication number 20020005537
- Publication date Jan 17, 2002
- Kuen-Chy Heo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating memory cell with vertical transistor
- Publication number 20010044189
- Publication date Nov 22, 2001
- Kuen-Chy Heo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating memory cell
- Publication number 20010044188
- Publication date Nov 22, 2001
- Kuen-Chy Heo
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of fabricating memory cell with trench capacitor and vertica...
- Publication number 20010044190
- Publication date Nov 22, 2001
- Kuen-Chy Heo
- H01 - BASIC ELECTRIC ELEMENTS