Kumar Lalgudi

Person

Fremont, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Logic cell structures and related methods
- Patent number 12,223,247
- Issue date Feb 11, 2025
- Taiwan Semiconductor Manufacturing Company Ltd.
- Kumar Lalgudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Logic cell structures and related methods
- Patent number 11,816,412
- Issue date Nov 14, 2023
- Taiwan Semiconductor Manufacturing Company Ltd.
- Kumar Lalgudi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Tapering discrete interconnection for an integrated circuit (IC)
- Patent number 11,239,163
- Issue date Feb 1, 2022
- Taiwan Semiconductor Manufacturing Co., Ltd
- Jaskirat Bindra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selectable delay buffers and logic cells for dynamic voltage scalin...
- Patent number 11,201,610
- Issue date Dec 14, 2021
- Taiwan Semiconductor Manufacturing Company Limited
- Jaskirat Bindra
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Selectable delay buffers and logic cells for dynamic voltage scalin...
- Patent number 10,819,325
- Issue date Oct 27, 2020
- Taiwan Semiconductor Manufacturing Company Limited
- Jaskirat Bindra
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tapering discrete interconnection for an integrated circuit (IC)
- Patent number 10,748,849
- Issue date Aug 18, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Jaskirat Bindra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques based on electromigration characteristics of cell interc...
- Patent number 10,678,990
- Issue date Jun 9, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Kuo-Nan Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selectable delay buffers and logic cells for dynamic voltage scalin...
- Patent number 10,476,490
- Issue date Nov 12, 2019
- Taiwan Semiconductor Manufacturing Company Limited
- Jaskirat Bindra
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Tapering discrete interconnection for an integrated circuit (IC)
- Patent number 10,276,497
- Issue date Apr 30, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Jaskirat Bindra
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Techniques based on electromigration characteristics of cell interc...
- Patent number 10,157,254
- Issue date Dec 18, 2018
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Kuo-Nan Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit having a staggered fishbone power network
- Patent number 9,799,602
- Issue date Oct 24, 2017
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Kuang-Hung Chang
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
LOGIC CELL STRUCTURES AND RELATED METHODS
- Publication number 20240012975
- Publication date Jan 11, 2024
- Taiwan Semiconductor Manufacturing company Ltd.
- KUMAR LALGUDI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LOGIC CELL STRUCTURES AND RELATED METHODS
- Publication number 20220335191
- Publication date Oct 20, 2022
- Taiwan Semiconductor Manufacturing company Ltd.
- KUMAR LALGUDI
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Selectable Delay Buffers and Logic Cells for Dynamic Voltage Scalin...
- Publication number 20210028776
- Publication date Jan 28, 2021
- Taiwan Semiconductor Manufacturing Company Limited
- Jaskirat Bindra
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TAPERING DISCRETE INTERCONNECTION FOR AN INTEGRATED CIRCUIT (IC)
- Publication number 20200357735
- Publication date Nov 12, 2020
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Jaskirat BINDRA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Selectable Delay Buffers and Logic Cells for Dynamic Voltage Scalin...
- Publication number 20200036368
- Publication date Jan 30, 2020
- Taiwan Semiconductor Manufacturing Company Limited
- Jaskirat Bindra
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
TAPERING DISCRETE INTERCONNECTION FOR AN INTEGRATED CIRCUIT (IC)
- Publication number 20190252309
- Publication date Aug 15, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Jaskirat BINDRA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES BASED ON ELECTROMIGRATION CHARACTERISTICS OF CELL INTERC...
- Publication number 20190108304
- Publication date Apr 11, 2019
- Taiwan Semiconductor Manufacturing Co., LTD
- Kuo-Nan Yang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TAPERING DISCRETE INTERCONNECTION FOR AN INTEGRATED CIRCUIT (IC)
- Publication number 20190096799
- Publication date Mar 28, 2019
- Taiwan Semiconductor Manufacturing Co., Ltd.
- Jaskirat BINDRA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Selectable Delay Buffers and Logic Cells for Dynamic Voltage Scalin...
- Publication number 20180108388
- Publication date Apr 19, 2018
- Taiwan Semiconductor Manufacturing Company Limited
- Jaskirat Bindra
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATED CIRCUIT HAVING A STAGGERED FISHBONE POWER NETWORK
- Publication number 20170194252
- Publication date Jul 6, 2017
- TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
- Kuang-Hung CHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TECHNIQUES BASED ON ELECTROMIGRATION CHARACTERISTICS OF CELL INTERC...
- Publication number 20170186691
- Publication date Jun 29, 2017
- Taiwan Semiconductor Manufacturing Co., LTD
- Kuo-Nan Yang
- G06 - COMPUTING CALCULATING COUNTING

Kumar Lalgudi

Person

Patents Grantslast 30 patents

Logic cell structures and related methods

Logic cell structures and related methods

Tapering discrete interconnection for an integrated circuit (IC)

Selectable delay buffers and logic cells for dynamic voltage scalin...

Selectable delay buffers and logic cells for dynamic voltage scalin...

Tapering discrete interconnection for an integrated circuit (IC)

Techniques based on electromigration characteristics of cell interc...

Selectable delay buffers and logic cells for dynamic voltage scalin...

Tapering discrete interconnection for an integrated circuit (IC)

Techniques based on electromigration characteristics of cell interc...

Integrated circuit having a staggered fishbone power network

Patents Applicationslast 30 patents

LOGIC CELL STRUCTURES AND RELATED METHODS

LOGIC CELL STRUCTURES AND RELATED METHODS

Selectable Delay Buffers and Logic Cells for Dynamic Voltage Scalin...

TAPERING DISCRETE INTERCONNECTION FOR AN INTEGRATED CIRCUIT (IC)

Selectable Delay Buffers and Logic Cells for Dynamic Voltage Scalin...

TAPERING DISCRETE INTERCONNECTION FOR AN INTEGRATED CIRCUIT (IC)

TECHNIQUES BASED ON ELECTROMIGRATION CHARACTERISTICS OF CELL INTERC...

TAPERING DISCRETE INTERCONNECTION FOR AN INTEGRATED CIRCUIT (IC)

Selectable Delay Buffers and Logic Cells for Dynamic Voltage Scalin...

INTEGRATED CIRCUIT HAVING A STAGGERED FISHBONE POWER NETWORK

TECHNIQUES BASED ON ELECTROMIGRATION CHARACTERISTICS OF CELL INTERC...