Kun-Lun Luo

Person

Hsinchu City, TW

People

Patents Grantslast 30 patents

Information Patent Grant
Device and method for generating input control signals of a seriali...
- Patent number 9,459,319
- Issue date Oct 4, 2016
- Industrial Technology Research Institute
- Chen-An Chen
- G01 - MEASURING TESTING
Information Patent Grant
Repairable multi-layer memory chip stack and method thereof
- Patent number 8,867,286
- Issue date Oct 21, 2014
- Industrial Technology Research Institute
- Ming-Hsueh Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Test device and method for the SoC test architecture
- Patent number 8,555,123
- Issue date Oct 8, 2013
- Industrial Technology Research Institute
- Ming-Hsueh Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Test device and method for hierarchical test architecture
- Patent number 8,185,782
- Issue date May 22, 2012
- Industrial Technology Research Institute
- Kun-Lun Luo
- G01 - MEASURING TESTING
Information Patent Grant
Method and apparatus of build-in self-diagnosis and repair in a mem...
- Patent number 7,644,323
- Issue date Jan 5, 2010
- Industrial Technology Research Institute
- Cheng-Wen Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Wrapper testing circuits and method thereof for system-on-a-chip
- Patent number 7,506,231
- Issue date Mar 17, 2009
- Industrial Technology Research Institute
- Yeong-Jar Chang
- G01 - MEASURING TESTING
Information Patent Grant
Built-in memory current test circuit
- Patent number 7,319,625
- Issue date Jan 15, 2008
- Industrial Technology Research Institute
- Yeong-Jar Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Method and apparatus of build-in self-diagnosis and repair in a mem...
- Patent number 7,228,468
- Issue date Jun 5, 2007
- Industrial Technology Research Institute
- Cheng-Wen Wu
- G11 - INFORMATION STORAGE
Information Patent Grant
Built-in jitter measurement circuit for voltage controlled oscillat...
- Patent number 6,937,106
- Issue date Aug 30, 2005
- Industrial Technology Research Institute
- Yeong-Jar Chang
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
DEVICE AND METHOD FOR GENERATING INPUT CONTROL SIGNALS OF A SERIALI...
- Publication number 20150036783
- Publication date Feb 5, 2015
- Industrial Technology Research Institute
- Chen-An Chen
- G01 - MEASURING TESTING
Information Patent Application
REPAIRABLE MULTI-LAYER MEMORY CHIP STACK AND METHOD THEREOF
- Publication number 20130155794
- Publication date Jun 20, 2013
- Industrial Technology Research Institute
- Ming-Hsueh Wu
- G11 - INFORMATION STORAGE
Information Patent Application
Test Device and Method for the SoC Test Architecture
- Publication number 20120159251
- Publication date Jun 21, 2012
- Industrial Technology Research Institute
- Ming-Hsueh Wu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST DEVICE AND METHOD FOR THE SOC TEST ARCHITECTURE
- Publication number 20100023807
- Publication date Jan 28, 2010
- Industrial Technology Research Institute
- Ming-Shae WU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TEST DEVICE AND METHOD FOR HIERARCHICAL TEST ARCHITECTURE
- Publication number 20090259889
- Publication date Oct 15, 2009
- Industrial Technology Research Institute
- Kun-Lun Luo
- G01 - MEASURING TESTING
Information Patent Application
Scan Test Data Compression Method And Decoding Apparatus For Multip...
- Publication number 20080133990
- Publication date Jun 5, 2008
- Shih-Ping Lin
- G01 - MEASURING TESTING
Information Patent Application
Method And Apparatus Of Build-In Self-Diagnosis And Repair In A Mem...
- Publication number 20070288807
- Publication date Dec 13, 2007
- Cheng-Wen Wu
- G11 - INFORMATION STORAGE
Information Patent Application
Wrapper testing circuits and method thereof for system-on-a-chip
- Publication number 20070255986
- Publication date Nov 1, 2007
- INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- Yeong-Jar Chang
- G01 - MEASURING TESTING
Information Patent Application
Built-in memory current test circuit
- Publication number 20070153597
- Publication date Jul 5, 2007
- INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- Yeong-Jar Chang
- G11 - INFORMATION STORAGE
Information Patent Application
Wrapper testing circuits and method thereof for system-on-a-chip
- Publication number 20060156104
- Publication date Jul 13, 2006
- INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
- Yeong-Jar Chang
- G01 - MEASURING TESTING
Information Patent Application
Method and apparatus of build-in self-diagnosis and repair in a mem...
- Publication number 20060064618
- Publication date Mar 23, 2006
- Cheng-Wen Wu
- G11 - INFORMATION STORAGE
Information Patent Application
Built-in jitter measurement circuit for voltage controlled oscillat...
- Publication number 20050057312
- Publication date Mar 17, 2005
- Industrial Technology Research Institute
- Yeong-Jar Chang
- H03 - BASIC ELECTRONIC CIRCUITRY

Kun-Lun Luo

Person

Patents Grantslast 30 patents

Device and method for generating input control signals of a seriali...

Repairable multi-layer memory chip stack and method thereof

Test device and method for the SoC test architecture

Test device and method for hierarchical test architecture

Method and apparatus of build-in self-diagnosis and repair in a mem...

Wrapper testing circuits and method thereof for system-on-a-chip

Built-in memory current test circuit

Method and apparatus of build-in self-diagnosis and repair in a mem...

Built-in jitter measurement circuit for voltage controlled oscillat...

Patents Applicationslast 30 patents

DEVICE AND METHOD FOR GENERATING INPUT CONTROL SIGNALS OF A SERIALI...

REPAIRABLE MULTI-LAYER MEMORY CHIP STACK AND METHOD THEREOF

Test Device and Method for the SoC Test Architecture

TEST DEVICE AND METHOD FOR THE SOC TEST ARCHITECTURE

TEST DEVICE AND METHOD FOR HIERARCHICAL TEST ARCHITECTURE

Scan Test Data Compression Method And Decoding Apparatus For Multip...

Method And Apparatus Of Build-In Self-Diagnosis And Repair In A Mem...

Wrapper testing circuits and method thereof for system-on-a-chip

Built-in memory current test circuit

Wrapper testing circuits and method thereof for system-on-a-chip

Method and apparatus of build-in self-diagnosis and repair in a mem...

Built-in jitter measurement circuit for voltage controlled oscillat...