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Kwangsoo Han
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Austin, TX, US
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last 30 patents
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Patent Grant
Multi-dimension clock gate design in clock tree synthesis
Patent number
10,963,618
Issue date
Mar 30, 2021
Cadence Design Systems, Ine.
Amin Farshidi
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Waveform propagation timing modeling for circuit design
Patent number
10,796,049
Issue date
Oct 6, 2020
Cadence Design Systems, Inc.
Kwangsoo Han
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
View pruning for routing tree optimization
Patent number
10,643,019
Issue date
May 5, 2020
Cadence Design Systems, Inc.
Kwangsoo Han
G06 - COMPUTING CALCULATING COUNTING
Information
Patent Grant
Honoring pin insertion delay during clock tree synthesis
Patent number
10,614,261
Issue date
Apr 7, 2020
Cadence Design Systems, Inc.
Michael Alexander
G06 - COMPUTING CALCULATING COUNTING