Kwen Siong Chong

Person

Singapore, SG

People

Patents Grantslast 30 patents

Information Patent Grant
Circuit for mitigating single-event-transients
- Patent number 12,294,363
- Issue date May 6, 2025
- ZERO-ERROR SYSTEMS PTE LTD
- Joseph Sylvester Chang
- G11 - INFORMATION STORAGE
Information Patent Grant
Integrated circuit layout cell, integrated circuit layout arrangeme...
- Patent number 11,695,011
- Issue date Jul 4, 2023
- Nanyang Technological University
- Kwen Siong Chong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Circuit arrangements and methods for forming the same
- Patent number 11,356,094
- Issue date Jun 7, 2022
- Nanyang Technological University
- Joseph Sylvester Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Hardware security to countermeasure side-channel attacks
- Patent number 11,227,071
- Issue date Jan 18, 2022
- Nanyang Technological University
- Kwen Siong Chong
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Circuit, method for sizing an aspect ratio of transistors of a circ...
- Patent number 11,177,807
- Issue date Nov 16, 2021
- ZERO-ERROR SYSTEMS PTE LTD
- Joseph Sylvester Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Circuit and method of forming the same
- Patent number 10,930,646
- Issue date Feb 23, 2021
- ZERO-ERROR SYSTEMS PTE LTD
- Joseph Sylvester Chang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Digital cell
- Patent number 8,994,406
- Issue date Mar 31, 2015
- Nanyang Technological University
- Joseph Sylvester Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Asynchronous-logic circuit for full dynamic voltage control
- Patent number 8,791,717
- Issue date Jul 29, 2014
- Nanyang Technological University
- Joseph Sylvester Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital multiplier with reduced spurious switching by means of Latc...
- Patent number 7,206,801
- Issue date Apr 17, 2007
- Chang, Joseph Sylvester
- Joseph Sylvester Chang
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ANOMALY DETECTION AND PROTECTION
- Publication number 20230288470
- Publication date Sep 14, 2023
- ZERO-ERROR SYSTEMS PTE. LTD.
- Joseph Sylvester CHANG
- G01 - MEASURING TESTING
Information Patent Application
A DEVICE AND METHOD FOR CHARGING ENERGY STORAGE DEVICES
- Publication number 20230261495
- Publication date Aug 17, 2023
- ZERO-ERROR SYSTEMS PTE. LTD.
- Wei SHU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUIT FOR MITIGATING SINGLE-EVENT-TRANSIENTS
- Publication number 20220368327
- Publication date Nov 17, 2022
- ZERO-ERROR SYSTEMS PTE. LTD.
- Joseph Sylvester CHANG
- G11 - INFORMATION STORAGE
Information Patent Application
SWITCHED-MODE POWER MODULE, A CONTROL CIRCUITRY THEREOF AND A POWER...
- Publication number 20220368220
- Publication date Nov 17, 2022
- ZERO-ERROR SYSTEMS PTE. LTD.
- Joseph Sylvester CHANG
- H02 - GENERATION CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
Information Patent Application
CIRCUIT ARRANGEMENTS AND METHODS FOR FORMING THE SAME
- Publication number 20210083665
- Publication date Mar 18, 2021
- Nanyang Technological University
- Joseph Sylvester CHANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUIT, METHOD FOR SIZING AN ASPECT RATIO OF TRANSISTORS OF A CIRC...
- Publication number 20210058083
- Publication date Feb 25, 2021
- Nanyang Technological University
- Joseph Sylvester CHANG
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
INTEGRATED CIRCUIT LAYOUT CELL, INTEGRATED CIRCUIT LAYOUT ARRANGEME...
- Publication number 20210050351
- Publication date Feb 18, 2021
- Nanyang Technological University
- Kwen Siong CHONG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CIRCUIT AND METHOD OF FORMING THE SAME
- Publication number 20200126971
- Publication date Apr 23, 2020
- Nanyang Technological University
- Joseph Sylvester Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
HARDWARE SECURITY TO COUNTERMEASURE SIDE-CHANNEL ATTACKS
- Publication number 20200004992
- Publication date Jan 2, 2020
- Nanyang Technological University
- Kwen Siong CHONG
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIGITAL CELL
- Publication number 20130342253
- Publication date Dec 26, 2013
- Nanyang Technological University
- Joseph Sylvester Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
ASYNCHRONOUS-LOGIC CIRCUIT FOR FULL DYNAMIC VOLTAGE CONTROL
- Publication number 20130113522
- Publication date May 9, 2013
- Nanyang Technological University
- Joseph Sylvester Chang
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
Digital Multiplier with reduced spurious switching by means of Latc...
- Publication number 20030220957
- Publication date Nov 27, 2003
- Joseph Sylvester Chang
- G06 - COMPUTING CALCULATING COUNTING

Kwen Siong Chong

Person

Patents Grantslast 30 patents

Circuit for mitigating single-event-transients

Integrated circuit layout cell, integrated circuit layout arrangeme...

Circuit arrangements and methods for forming the same

Hardware security to countermeasure side-channel attacks

Circuit, method for sizing an aspect ratio of transistors of a circ...

Circuit and method of forming the same

Digital cell

Asynchronous-logic circuit for full dynamic voltage control

Digital multiplier with reduced spurious switching by means of Latc...

Patents Applicationslast 30 patents

ANOMALY DETECTION AND PROTECTION

A DEVICE AND METHOD FOR CHARGING ENERGY STORAGE DEVICES

CIRCUIT FOR MITIGATING SINGLE-EVENT-TRANSIENTS

SWITCHED-MODE POWER MODULE, A CONTROL CIRCUITRY THEREOF AND A POWER...

CIRCUIT ARRANGEMENTS AND METHODS FOR FORMING THE SAME

CIRCUIT, METHOD FOR SIZING AN ASPECT RATIO OF TRANSISTORS OF A CIRC...

INTEGRATED CIRCUIT LAYOUT CELL, INTEGRATED CIRCUIT LAYOUT ARRANGEME...

CIRCUIT AND METHOD OF FORMING THE SAME

HARDWARE SECURITY TO COUNTERMEASURE SIDE-CHANNEL ATTACKS

DIGITAL CELL

ASYNCHRONOUS-LOGIC CIRCUIT FOR FULL DYNAMIC VOLTAGE CONTROL

Digital Multiplier with reduced spurious switching by means of Latc...