KYRIAKOS STAVROU

Person

BARCELONA, ES

People

Patents Grantslast 30 patents

Information Patent Grant
Instruction and logic for optimization level aware branch prediction
- Patent number 10,157,063
- Issue date Dec 18, 2018
- Intel Corporation
- Polychronis Xekalakis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Propagating a prefetching profile bit from a prefetch queue to a da...
- Patent number 10,013,326
- Issue date Jul 3, 2018
- Intel Corporation
- Raul Martinez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managed instruction cache prefetching
- Patent number 9,811,341
- Issue date Nov 7, 2017
- Intel Corporation
- Kyriakos A. Stavrou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Combined floating point multiplier adder with intermediate rounding...
- Patent number 9,389,871
- Issue date Jul 12, 2016
- Intel Corporation
- Marc Lupon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Image signal processor with a block checking circuit
- Patent number 9,374,542
- Issue date Jun 21, 2016
- Intel Corporation
- Kyriakos Stavrou
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Mechanism for facilitating dynamic and efficient fusion of computin...
- Patent number 9,329,848
- Issue date May 3, 2016
- Intel Corporation
- Marc Lupon
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Split-word memory
- Patent number 9,189,240
- Issue date Nov 17, 2015
- Intel Corporation
- Lutz Naethke
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Partial commits in dynamic binary translation based systems
- Patent number 9,116,719
- Issue date Aug 25, 2015
- Intel Corporation
- Raul Martinez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Split-word memory
- Patent number 8,924,660
- Issue date Dec 30, 2014
- Intel Corporation
- Lutz Naethke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Split-word memory
- Patent number 8,719,519
- Issue date May 6, 2014
- Intel Corporation
- Lutz Naethke
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
PROFILING ASYNCHRONOUS EVENTS RESULTING FROM THE EXECUTION OF SOFTW...
- Publication number 20190004916
- Publication date Jan 3, 2019
- Intel Corporation
- Raul Martinez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
IMAGE SIGNAL PROCESSOR WITH A BLOCK CHECKING CIRCUIT
- Publication number 20150281602
- Publication date Oct 1, 2015
- Intel Corporation
- KYRIAKOS STAVROU
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Split-Word Memory
- Publication number 20150081975
- Publication date Mar 19, 2015
- Intel Corporation
- Lutz Naethke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MECHANISM FOR FACILITATING DYNAMIC AND EFFICIENT FUSION OF COMPUTIN...
- Publication number 20150026671
- Publication date Jan 22, 2015
- Marc Lupon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARTIAL COMMITS IN DYNAMIC BINARY TRANSLATION BASED SYSTEMS
- Publication number 20150007153
- Publication date Jan 1, 2015
- Raul Martinez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMBINED FLOATING POINT MULTIPLIER ADDER WITH INTERMEDIATE ROUNDING...
- Publication number 20140281419
- Publication date Sep 18, 2014
- Intel Corporation
- Marc Lupon
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Split-Word Memory
- Publication number 20140208033
- Publication date Jul 24, 2014
- Lutz Naethke
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD, APPARATUS AND SYSTEM FOR SELECTIVE EXECUTION OF A COMMIT IN...
- Publication number 20140156976
- Publication date Jun 5, 2014
- Enric Gibert Codina
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INSTRUCTION AND LOGIC FOR OPTIMIZATION LEVEL AWARE BRANCH PREDICTION
- Publication number 20140095849
- Publication date Apr 3, 2014
- Polychronis Xekalakis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGED INSTRUCTION CACHE PREFETCHING
- Publication number 20140019721
- Publication date Jan 16, 2014
- Kyriakos A. Stavrou
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROFILING ASYNCHRONOUS EVENTS RESULTING FROM THE EXECUTION OF SOFTW...
- Publication number 20130332705
- Publication date Dec 12, 2013
- Raul Martinez
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CONTROLLING A MXCSR
- Publication number 20130326199
- Publication date Dec 5, 2013
- Grigorios Magklis
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORT FOR SPECULATIVE OWNERSHIP WITHOUT DATA
- Publication number 20130268735
- Publication date Oct 10, 2013
- Enric Gibert Codina
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SPLIT-WORD MEMORY
- Publication number 20130262793
- Publication date Oct 3, 2013
- Intel Corporation
- Lutz NAETHKE
- G06 - COMPUTING CALCULATING COUNTING

KYRIAKOS STAVROU

Person

Patents Grantslast 30 patents

Instruction and logic for optimization level aware branch prediction

Propagating a prefetching profile bit from a prefetch queue to a da...

Managed instruction cache prefetching

Combined floating point multiplier adder with intermediate rounding...

Image signal processor with a block checking circuit

Mechanism for facilitating dynamic and efficient fusion of computin...

Split-word memory

Partial commits in dynamic binary translation based systems

Split-word memory

Split-word memory

Patents Applicationslast 30 patents

PROFILING ASYNCHRONOUS EVENTS RESULTING FROM THE EXECUTION OF SOFTW...

IMAGE SIGNAL PROCESSOR WITH A BLOCK CHECKING CIRCUIT

Split-Word Memory

MECHANISM FOR FACILITATING DYNAMIC AND EFFICIENT FUSION OF COMPUTIN...

PARTIAL COMMITS IN DYNAMIC BINARY TRANSLATION BASED SYSTEMS

COMBINED FLOATING POINT MULTIPLIER ADDER WITH INTERMEDIATE ROUNDING...

Split-Word Memory

METHOD, APPARATUS AND SYSTEM FOR SELECTIVE EXECUTION OF A COMMIT IN...

INSTRUCTION AND LOGIC FOR OPTIMIZATION LEVEL AWARE BRANCH PREDICTION

MANAGED INSTRUCTION CACHE PREFETCHING

PROFILING ASYNCHRONOUS EVENTS RESULTING FROM THE EXECUTION OF SOFTW...

METHOD AND APPARATUS FOR CONTROLLING A MXCSR

SUPPORT FOR SPECULATIVE OWNERSHIP WITHOUT DATA

SPLIT-WORD MEMORY