Laegu Kang

Person

Hopewell Junction, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Transistor device structures with retrograde wells in CMOS applicat...
- Patent number 10,483,172
- Issue date Nov 19, 2019
- GLOBALFOUNDRIES Inc.
- Vara G. Reddy Vakada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming transistors with retrograde wells in CMOS applic...
- Patent number 9,852,954
- Issue date Dec 26, 2017
- GLOBALFOUNDRIES Inc.
- Vara G. Reddy Vakada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Blanket EPI super steep retrograde well formation without Si recess
- Patent number 9,362,357
- Issue date Jun 7, 2016
- GLOBALFOUNDRIES Inc.
- Laegu Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming transistors with retrograde wells in CMOS applic...
- Patent number 9,209,181
- Issue date Dec 8, 2015
- GLOBALFOUNDRIES Inc.
- Vara G. Reddy Vakada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Blanket EPI super steep retrograde well formation without Si recess
- Patent number 9,099,525
- Issue date Aug 4, 2015
- GLOBALFOUNDRIES Inc.
- Laegu Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming step doping channel profile for super steep retro...
- Patent number 9,099,380
- Issue date Aug 4, 2015
- GLOBALFOUNDRIES Inc.
- Vara Govindeswara Reddy Vakada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming step doping channel profile for super steep retro...
- Patent number 8,916,442
- Issue date Dec 23, 2014
- GLOBALFOUNDRIES Inc.
- Vara Govindeswara Reddy Vakada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming bulk FinFET devices with replacement gates so as...
- Patent number 8,809,178
- Issue date Aug 19, 2014
- GLOBALFOUNDRIES Inc.
- Yanxiang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Methods of forming CMOS transistors using tensile stress layers and...
- Patent number 8,790,972
- Issue date Jul 29, 2014
- Samsung Electronics Co., Ltd.
- Yong-Kuk Jeong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High pressure deuterium treatment for semiconductor/high-K insulato...
- Patent number 8,445,969
- Issue date May 21, 2013
- FREESCALE SEMICONDUCTOR, INC.
- Xiangdong Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Balancing NFET and PFET performance using straining layers
- Patent number 8,106,462
- Issue date Jan 31, 2012
- International Business Machines Corporation
- Xiangdong Chen
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
TRANSISTOR DEVICE STRUCTURES WITH RETROGRADE WELLS IN CMOS APPLICAT...
- Publication number 20180047641
- Publication date Feb 15, 2018
- GLOBALFOUNDRIES INC.
- Vara G. Reddy Vakada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING TRANSISTORS WITH RETROGRADE WELLS IN CMOS APPLIC...
- Publication number 20160035630
- Publication date Feb 4, 2016
- GLOBALFOUNDRIES INC.
- Vara G. Reddy Vakada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BLANKET EPI SUPER STEEP RETROGRADE WELL FORMATION WITHOUT Si RECESS
- Publication number 20150249129
- Publication date Sep 3, 2015
- GLOBALFOUNDRIES INC.
- Laegu KANG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING STEP DOPING CHANNEL PROFILE FOR SUPER STEEP RETRO...
- Publication number 20150053981
- Publication date Feb 26, 2015
- GLOBALFOUNDRIES INC.
- Vara Govindeswara Reddy Vakada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING TRANSISTORS WITH RETROGRADE WELLS IN CMOS APPLIC...
- Publication number 20140367787
- Publication date Dec 18, 2014
- Vara G. Reddy Vakada
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF FORMING STEP DOPING CHANNEL PROFILE FOR SUPER STEEP RETRO...
- Publication number 20140197411
- Publication date Jul 17, 2014
- GLOBAL FOUNDERIES INC.
- Vara Govindeswara Reddy VAKADA
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BLANKET EPI SUPER STEEP RETROGRADE WELL FORMATION WITHOUT Si RECESS
- Publication number 20140183551
- Publication date Jul 3, 2014
- GLOBALFOUNDRIES INC.
- Laegu Kang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF TAILORING SILICON TRENCH PROFILE FOR SUPER STEEP RETROGRA...
- Publication number 20140070358
- Publication date Mar 13, 2014
- GLOBALFOUNDRIES INC.
- Yi Qi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHODS OF FORMING BULK FINFET DEVICES WITH REPLACEMENT GATES SO AS...
- Publication number 20130224945
- Publication date Aug 29, 2013
- GLOBALFOUNDRIES INC.
- Yanxiang Liu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH PRESSURE DEUTERIUM TREATMENT FOR SEMICONDUCTOR/HIGH-K INSULATO...
- Publication number 20120273894
- Publication date Nov 1, 2012
- International Business Machines Corporation
- Xiangdong Chen
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Methods of Forming CMOS Transistors Using Tensile Stress Layers and...
- Publication number 20120045873
- Publication date Feb 23, 2012
- Yong-Kuk Jeong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERS
- Publication number 20110169096
- Publication date Jul 14, 2011
- International Business Machines Corporation
- Xiangdong Chen
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Transistor device structures with retrograde wells in CMOS applicat...

Methods of forming transistors with retrograde wells in CMOS applic...

Blanket EPI super steep retrograde well formation without Si recess

Methods of forming transistors with retrograde wells in CMOS applic...

Blanket EPI super steep retrograde well formation without Si recess

Method of forming step doping channel profile for super steep retro...

Method of forming step doping channel profile for super steep retro...

Methods of forming bulk FinFET devices with replacement gates so as...

Methods of forming CMOS transistors using tensile stress layers and...

High pressure deuterium treatment for semiconductor/high-K insulato...

Balancing NFET and PFET performance using straining layers

Patents Applicationslast 30 patents

TRANSISTOR DEVICE STRUCTURES WITH RETROGRADE WELLS IN CMOS APPLICAT...

METHODS OF FORMING TRANSISTORS WITH RETROGRADE WELLS IN CMOS APPLIC...

BLANKET EPI SUPER STEEP RETROGRADE WELL FORMATION WITHOUT Si RECESS

METHOD OF FORMING STEP DOPING CHANNEL PROFILE FOR SUPER STEEP RETRO...

METHODS OF FORMING TRANSISTORS WITH RETROGRADE WELLS IN CMOS APPLIC...

METHOD OF FORMING STEP DOPING CHANNEL PROFILE FOR SUPER STEEP RETRO...

BLANKET EPI SUPER STEEP RETROGRADE WELL FORMATION WITHOUT Si RECESS

METHOD OF TAILORING SILICON TRENCH PROFILE FOR SUPER STEEP RETROGRA...

METHODS OF FORMING BULK FINFET DEVICES WITH REPLACEMENT GATES SO AS...

HIGH PRESSURE DEUTERIUM TREATMENT FOR SEMICONDUCTOR/HIGH-K INSULATO...

Methods of Forming CMOS Transistors Using Tensile Stress Layers and...

BALANCING NFET AND PFET PERFORMANCE USING STRAINING LAYERS