Lakshmipriya Seshan

Person

Santa Clara, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Approximate data bus inversion technique for latency sensitive appl...
- Patent number 12,117,960
- Issue date Oct 15, 2024
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Link layer-PHY interface adapter
- Patent number 11,971,841
- Issue date Apr 30, 2024
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Clock phase compensation apparatus and method
- Patent number 10,686,582
- Issue date Jun 16, 2020
- Intel Corporation
- Gerald Pasdast
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
ASSYMMETRICAL DATA RATES FOR HIGH SPEED INTERCONNECTS
- Publication number 20240095206
- Publication date Mar 21, 2024
- Intel Corporation
- Sampath Dakshinamurthy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
TECHNIQUES TO PERFORM SEMICONDUCTOR TESTING
- Publication number 20230258716
- Publication date Aug 17, 2023
- Intel Corporation
- Swadesh Choudhary
- G01 - MEASURING TESTING
Information Patent Application
PERFORMANCE LEVEL CONTROL IN A DATA PROCESSING APPARATUS
- Publication number 20230236651
- Publication date Jul 27, 2023
- Intel Corporation
- UJJWAL GUPTA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MICROELECTRONIC DIE INCLUDING SWAPPABLE PHY CIRCUITRY AND SEMICONDU...
- Publication number 20230230923
- Publication date Jul 20, 2023
- Intel Corporation
- Gerald Pasdast
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIE-TO-DIE INTERCONNECT
- Publication number 20220342840
- Publication date Oct 27, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE-TO-DIE ADAPTER
- Publication number 20220342841
- Publication date Oct 27, 2022
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
RETIMERS TO EXTEND A DIE-TO-DIE INTERCONNECT
- Publication number 20220334932
- Publication date Oct 20, 2022
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PARAMETER EXCHANGE FOR A DIE-TO-DIE INTERCONNECT
- Publication number 20220334995
- Publication date Oct 20, 2022
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LANE REPAIR AND LANE REVERSAL IMPLEMENTATION FOR DIE-TO-DIE (D2D) I...
- Publication number 20220327276
- Publication date Oct 13, 2022
- Intel Corporation
- Lakshmipriya Seshan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIE-TO-DIE INTERCONNECT PROTOCOL LAYER
- Publication number 20220327084
- Publication date Oct 13, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS
- Publication number 20220327083
- Publication date Oct 13, 2022
- Intel Corporation
- Debendra Das Sharma
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMPLIANCE AND DEBUG TESTING OF A DIE-TO-DIE INTERCONNECT
- Publication number 20220318111
- Publication date Oct 6, 2022
- Intel Corporation
- Swadesh Choudhary
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CLOCK PHASE MANAGEMENT FOR DIE-TO-DIE (D2D) INTERCONNECT
- Publication number 20220271912
- Publication date Aug 25, 2022
- Gerald Pasdast
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CLOCK-GATING IN DIE-TO-DIE (D2D) INTERCONNECTS
- Publication number 20220262756
- Publication date Aug 18, 2022
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
VALID SIGNAL FOR LATENCY SENSITIVE DIE-TO-DIE (D2D) INTERCONNECTS
- Publication number 20220261308
- Publication date Aug 18, 2022
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK INITIALIZATION TRAINING AND BRING UP FOR DIE-TO-DIE INTERCONNECT
- Publication number 20220237138
- Publication date Jul 28, 2022
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SIDEBAND INTERFACE FOR DIE-TO-DIE INTERCONNECTS
- Publication number 20220222198
- Publication date Jul 14, 2022
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCALABLE AND INTEROPERABLE PHYLESS DIE-TO-DIE IO SOLUTION
- Publication number 20210398906
- Publication date Dec 23, 2021
- Intel Corporation
- Zhiguo QIAN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PHY-BASED RETRY TECHNIQUES FOR DIE-TO-DIE INTERFACES
- Publication number 20210344354
- Publication date Nov 4, 2021
- Intel Corporation
- Narasimha Lanka
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
APPROXIMATE DATA BUS INVERSION TECHNIQUE FOR LATENCY SENSITIVE APPL...
- Publication number 20210004347
- Publication date Jan 7, 2021
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LINK LAYER-PHY INTERFACE ADAPTER
- Publication number 20200394150
- Publication date Dec 17, 2020
- Intel Corporation
- Narasimha Lanka
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
STACKED MEMORY DEVICE WITH END TO END DATA BUS INVERSION
- Publication number 20200251159
- Publication date Aug 6, 2020
- Intel Corporation
- Narasimha Lanka
- G11 - INFORMATION STORAGE

Lakshmipriya Seshan

Person

Patents Grantslast 30 patents

Approximate data bus inversion technique for latency sensitive appl...

Link layer-PHY interface adapter

Clock phase compensation apparatus and method

Patents Applicationslast 30 patents

ASSYMMETRICAL DATA RATES FOR HIGH SPEED INTERCONNECTS

TECHNIQUES TO PERFORM SEMICONDUCTOR TESTING

PERFORMANCE LEVEL CONTROL IN A DATA PROCESSING APPARATUS

MICROELECTRONIC DIE INCLUDING SWAPPABLE PHY CIRCUITRY AND SEMICONDU...

DIE-TO-DIE INTERCONNECT

DIE-TO-DIE ADAPTER

RETIMERS TO EXTEND A DIE-TO-DIE INTERCONNECT

PARAMETER EXCHANGE FOR A DIE-TO-DIE INTERCONNECT

LANE REPAIR AND LANE REVERSAL IMPLEMENTATION FOR DIE-TO-DIE (D2D) I...

DIE-TO-DIE INTERCONNECT PROTOCOL LAYER

STANDARD INTERFACES FOR DIE TO DIE (D2D) INTERCONNECT STACKS

COMPLIANCE AND DEBUG TESTING OF A DIE-TO-DIE INTERCONNECT

CLOCK PHASE MANAGEMENT FOR DIE-TO-DIE (D2D) INTERCONNECT

CLOCK-GATING IN DIE-TO-DIE (D2D) INTERCONNECTS

VALID SIGNAL FOR LATENCY SENSITIVE DIE-TO-DIE (D2D) INTERCONNECTS

LINK INITIALIZATION TRAINING AND BRING UP FOR DIE-TO-DIE INTERCONNECT

SIDEBAND INTERFACE FOR DIE-TO-DIE INTERCONNECTS

SCALABLE AND INTEROPERABLE PHYLESS DIE-TO-DIE IO SOLUTION

PHY-BASED RETRY TECHNIQUES FOR DIE-TO-DIE INTERFACES

APPROXIMATE DATA BUS INVERSION TECHNIQUE FOR LATENCY SENSITIVE APPL...

LINK LAYER-PHY INTERFACE ADAPTER

STACKED MEMORY DEVICE WITH END TO END DATA BUS INVERSION