Lance C. Cheney

Person

El Dorado Hills, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Enabling product SKUs based on chiplet configurations
- Patent number 12,141,890
- Issue date Nov 12, 2024
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of system-on-chip (SOC) architecture
- Patent number 12,112,398
- Issue date Oct 8, 2024
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of system-on-chip (SOC) architecture
- Patent number 12,056,789
- Issue date Aug 6, 2024
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of system-on-chip (SOC) architecture
- Patent number 11,763,416
- Issue date Sep 19, 2023
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of system-on-chip (SOC) architecture
- Patent number 11,756,150
- Issue date Sep 12, 2023
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of System-On-Chip (SOC) architecture
- Patent number 11,410,266
- Issue date Aug 9, 2022
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enabling product SKUS based on chiplet configurations
- Patent number 11,386,521
- Issue date Jul 12, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enabling product SKUs based on chiplet configurations
- Patent number 10,909,652
- Issue date Feb 2, 2021
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Disaggregation of SOC architecture
- Patent number 10,803,548
- Issue date Oct 13, 2020
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Activating a design test mode in a graphics card having multiple ex...
- Patent number 7,904,701
- Issue date Mar 8, 2011
- Intel Corporation
- Anthony Babella
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Checking output from multiple execution units
- Patent number 7,793,187
- Issue date Sep 7, 2010
- Intel Corporation
- Allan Wong
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
- Publication number 20240013338
- Publication date Jan 11, 2024
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
- Publication number 20240005443
- Publication date Jan 4, 2024
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS
- Publication number 20220188967
- Publication date Jun 16, 2022
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
- Publication number 20220180468
- Publication date Jun 9, 2022
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE
- Publication number 20220036500
- Publication date Feb 3, 2022
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS
- Publication number 20210256654
- Publication date Aug 19, 2021
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATION OF SOC ARCHITECTURE
- Publication number 20210133913
- Publication date May 6, 2021
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DISAGGREGATION OF SOC ARCHITECTURE
- Publication number 20200294181
- Publication date Sep 17, 2020
- Intel Corporation
- Naveen Matam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS
- Publication number 20200294180
- Publication date Sep 17, 2020
- Intel Corporation
- Altug Koker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR TUNING SCAN CAPTURE PHASE ACTIVITY FACTOR
- Publication number 20140181603
- Publication date Jun 26, 2014
- Iwan R. Grau
- G01 - MEASURING TESTING
Information Patent Application
ACTIVATING A DESIGN TEST MODE IN A GRAPHICS CARD HAVING MULTIPLE EX...
- Publication number 20080307261
- Publication date Dec 11, 2008
- Anthony BABELLA
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CHECKING OUTPUT FROM MULTIPLE EXECUTION UNITS
- Publication number 20080307275
- Publication date Dec 11, 2008
- Allan WONG
- G06 - COMPUTING CALCULATING COUNTING

Lance C. Cheney

Person

Patents Grantslast 30 patents

Enabling product SKUs based on chiplet configurations

Disaggregation of system-on-chip (SOC) architecture

Disaggregation of system-on-chip (SOC) architecture

Disaggregation of system-on-chip (SOC) architecture

Disaggregation of system-on-chip (SOC) architecture

Disaggregation of System-On-Chip (SOC) architecture

Enabling product SKUS based on chiplet configurations

Enabling product SKUs based on chiplet configurations

Disaggregation of SOC architecture

Activating a design test mode in a graphics card having multiple ex...

Checking output from multiple execution units

Patents Applicationslast 30 patents

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

DISAGGREGATION OF SYSTEM-ON-CHIP (SOC) ARCHITECTURE

ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS

DISAGGREGATION OF SOC ARCHITECTURE

DISAGGREGATION OF SOC ARCHITECTURE

ENABLING PRODUCT SKUS BASED ON CHIPLET CONFIGURATIONS

METHOD AND APPARATUS FOR TUNING SCAN CAPTURE PHASE ACTIVITY FACTOR

ACTIVATING A DESIGN TEST MODE IN A GRAPHICS CARD HAVING MULTIPLE EX...

CHECKING OUTPUT FROM MULTIPLE EXECUTION UNITS