Lance S. Robertson

Person

Rockwall, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Divergent charged particle implantation for improved transistor sym...
- Patent number 7,807,978
- Issue date Oct 5, 2010
- Texas Instruments Incorporated
- James D. Bernstein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Matched analog CMOS transistors with extension wells
- Patent number 7,692,217
- Issue date Apr 6, 2010
- Texas Instruments Incorporated
- Henry Litzmann Edwards
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing dislocation threading using a suppression implant
- Patent number 7,638,415
- Issue date Dec 29, 2009
- Texas Instruments Incorporated
- Martin Mollat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for reducing dislocation threading using a suppression implant
- Patent number 7,466,009
- Issue date Dec 16, 2008
- Texas Instruments Incorporated
- Martin Mollat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for manufacturing a semiconductor device containing metal si...
- Patent number 7,422,967
- Issue date Sep 9, 2008
- Texas Instruments Incorporated
- Juanita DeLoach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Divergent charged particle implantation for improved transistor sym...
- Patent number 7,385,202
- Issue date Jun 10, 2008
- Texas Instruments Incorporated
- James D. Bernstein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicide formation using a low temperature anneal process
- Patent number 7,335,595
- Issue date Feb 26, 2008
- Texas Instruments Incorporated
- Lance S. Robertson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Implant optimization scheme
- Patent number 7,253,072
- Issue date Aug 7, 2007
- Texas Instruments Incorporated
- James D. Bernstein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for implanting dopants within a substrate by tilting the sub...
- Patent number 7,232,744
- Issue date Jun 19, 2007
- Texas Instruments Incorporated
- Said Ghneim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit metal silicide method
- Patent number 7,208,409
- Issue date Apr 24, 2007
- Texas Instruments Incorporated
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device having optimized shallow junction geometries a...
- Patent number 7,033,879
- Issue date Apr 25, 2006
- Texas Instruments Incorporated
- Brian E. Hornung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Silicide method for CMOS integrated circuits
- Patent number 7,029,967
- Issue date Apr 18, 2006
- Texas Instruments Incorporated
- Song Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Process for optimizing junctions formed by solid phase epitaxy
- Patent number 6,699,771
- Issue date Mar 2, 2004
- Texas Instruments Incorporated
- Lance S. Robertson
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
MATCHED ANALOG CMOS TRANSISTORS WITH EXTENSION WELLS
- Publication number 20090140346
- Publication date Jun 4, 2009
- Henry Litzmann Edwards
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR REDUCING DISLOCATION THREADING USING A SUPPRESSION IMPLANT
- Publication number 20090061606
- Publication date Mar 5, 2009
- TEXAS INSTRUMENTS INCORPORATED
- Martin Mollat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIVERGENT CHARGED PARTICLE IMPLANTATION FOR IMPROVED TRANSISTOR SYM...
- Publication number 20080206971
- Publication date Aug 28, 2008
- TEXAS INSTRUMENTS INCORPORATED
- James D. Bernstein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Divergent Charged Particle Implantation for Improved Transistor Sym...
- Publication number 20080142724
- Publication date Jun 19, 2008
- TEXAS INSTRUMENTS INCORPORATED
- James D. Bernstein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
A METHOD FOR REDUCING DISLOCATION THREADING USING A SUPPRESSION IMP...
- Publication number 20070281433
- Publication date Dec 6, 2007
- TEXAS INSTRUMENTS INCORPORATED
- Martin Mollat
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Implant Optimization Scheme
- Publication number 20070257211
- Publication date Nov 8, 2007
- TEXAS INSTRUMENTS INCORPORATED
- James D. Bernstein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Novel method for manufacturing a semiconductor device containing me...
- Publication number 20060258091
- Publication date Nov 16, 2006
- Texas Instruments Inc.
- Juanita DeLoach
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Divergent charged particle implantation for improved transistor sym...
- Publication number 20060121706
- Publication date Jun 8, 2006
- Texas Instruments, Inc.
- James D. Bernstein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for implanting dopants within a substrate by tilting the sub...
- Publication number 20060073685
- Publication date Apr 6, 2006
- TEXAS INSTRUMENTS INCORPORATED
- Said Ghneim
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicide method for CMOS integrated circuits
- Publication number 20060019478
- Publication date Jan 26, 2006
- Song Zhao
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Silicide formation using a low temperature anneal process
- Publication number 20060014387
- Publication date Jan 19, 2006
- Lance S. Robertson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device having optimized shallow junction geometries a...
- Publication number 20060001105
- Publication date Jan 5, 2006
- Brian E. Hornung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Implant optimization scheme
- Publication number 20050255683
- Publication date Nov 17, 2005
- TEXAS INSTRUMENTS INCORPORATED
- James D. Bernstein
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Semiconductor device having optimized shallow junction geometries a...
- Publication number 20050245021
- Publication date Nov 3, 2005
- Texas Instruments, Incorporated
- Brian E. Hornung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Integrated circuit metal silicide method
- Publication number 20050208764
- Publication date Sep 22, 2005
- Jiong-Ping Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Ultra shallow junction formation
- Publication number 20050112830
- Publication date May 26, 2005
- Amitabh Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Process for optimizing junctions formed by solid phase epitaxy
- Publication number 20040115892
- Publication date Jun 17, 2004
- Lance S. Robertson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Ultra shallow junction formation
- Publication number 20040115889
- Publication date Jun 17, 2004
- Amitabh Jain
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PROCESS FOR OPTIMIZING JUNCTIONS FORMED BY SOLID PHASE EPITAXY
- Publication number 20040029350
- Publication date Feb 12, 2004
- Lance S. Robertson
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Versatile system for forming shallow semiconductor device features
- Publication number 20030124821
- Publication date Jul 3, 2003
- Lance Stanford Robertson
- H01 - BASIC ELECTRIC ELEMENTS

Lance S. Robertson

Person

Patents Grantslast 30 patents

Divergent charged particle implantation for improved transistor sym...

Matched analog CMOS transistors with extension wells

Method for reducing dislocation threading using a suppression implant

Method for reducing dislocation threading using a suppression implant

Method for manufacturing a semiconductor device containing metal si...

Divergent charged particle implantation for improved transistor sym...

Silicide formation using a low temperature anneal process

Implant optimization scheme

Method for implanting dopants within a substrate by tilting the sub...

Integrated circuit metal silicide method

Semiconductor device having optimized shallow junction geometries a...

Silicide method for CMOS integrated circuits

Process for optimizing junctions formed by solid phase epitaxy

Patents Applicationslast 30 patents

MATCHED ANALOG CMOS TRANSISTORS WITH EXTENSION WELLS

METHOD FOR REDUCING DISLOCATION THREADING USING A SUPPRESSION IMPLANT

DIVERGENT CHARGED PARTICLE IMPLANTATION FOR IMPROVED TRANSISTOR SYM...

Divergent Charged Particle Implantation for Improved Transistor Sym...

A METHOD FOR REDUCING DISLOCATION THREADING USING A SUPPRESSION IMP...

Implant Optimization Scheme

Novel method for manufacturing a semiconductor device containing me...

Divergent charged particle implantation for improved transistor sym...

Method for implanting dopants within a substrate by tilting the sub...

Silicide method for CMOS integrated circuits

Silicide formation using a low temperature anneal process

Semiconductor device having optimized shallow junction geometries a...

Implant optimization scheme

Semiconductor device having optimized shallow junction geometries a...

Integrated circuit metal silicide method

Ultra shallow junction formation

Process for optimizing junctions formed by solid phase epitaxy

Ultra shallow junction formation

PROCESS FOR OPTIMIZING JUNCTIONS FORMED BY SOLID PHASE EPITAXY

Versatile system for forming shallow semiconductor device features