Larisa Novakovsky

Person

Haifa, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Apparatus and method to identify the source of an interrupt
- Patent number 11,900,115
- Issue date Feb 13, 2024
- Intel Corporation
- Ashok Raj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method to identify the source of an interrupt
- Patent number 11,614,939
- Issue date Mar 28, 2023
- Intel Corporation
- Ashok Raj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method to identify the source of an interrupt
- Patent number 11,048,512
- Issue date Jun 29, 2021
- Intel Corporation
- Ashok Raj
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System, apparatus and method for probeless field scan of a processor
- Patent number 10,775,434
- Issue date Sep 15, 2020
- Intel Corporation
- Michael Mishaeli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Supporting hang detection and data recovery in microprocessor systems
- Patent number 10,725,848
- Issue date Jul 28, 2020
- Intel Corporation
- Tsvika Kurts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Communicating via a mailbox interface of a processor
- Patent number 10,719,326
- Issue date Jul 21, 2020
- Intel Corporation
- Alexander Gendler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Core-only system management interrupt
- Patent number 10,628,542
- Issue date Apr 21, 2020
- Intel Corporation
- Tsvika Kurts
- G01 - MEASURING TESTING
Information Patent Grant
Systems and methods for enhancing BIOS performance by alleviating c...
- Patent number 10,175,992
- Issue date Jan 8, 2019
- Intel Corporation
- Leon Polishuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Pipelined prefetcher for parallel advancement of multiple data streams
- Patent number 10,157,136
- Issue date Dec 18, 2018
- Intel Corporation
- Leeor Peled
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for memory-hierarchy aware producer-consumer i...
- Patent number 9,990,287
- Issue date Jun 5, 2018
- Intel Corporation
- Shlomo Raikin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache memory staged reopen
- Patent number 9,830,272
- Issue date Nov 28, 2017
- Intel Corporation
- Iris Sorani
- G11 - INFORMATION STORAGE
Information Patent Grant
Masking a power state of a core of a processor
- Patent number 9,710,041
- Issue date Jul 18, 2017
- Intel Corporation
- Alexander Gendler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive hierarchical cache policy in a microprocessor
- Patent number 9,684,595
- Issue date Jun 20, 2017
- Intel Corporation
- Larisa Novakovsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method to transfer data packets between domains of a...
- Patent number 9,535,476
- Issue date Jan 3, 2017
- Intel Corporation
- Shani Rehana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Restricting clock signal delivery in a processor
- Patent number 9,471,088
- Issue date Oct 18, 2016
- Intel Corporation
- Alexander Gendler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for cache line write back operation
- Patent number 9,471,494
- Issue date Oct 18, 2016
- Intel Corporation
- Rajesh M. Sankaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Apparatus and method for implement a multi-level memory hierarchy
- Patent number 9,448,879
- Issue date Sep 20, 2016
- Intel Corporation
- Theodros Yigzaw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Adaptive hierarchical cache policy in a microprocessor
- Patent number 9,378,148
- Issue date Jun 28, 2016
- Intel Corporation
- Larisa Novakovsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Cache circuit having a tag array with smaller latency than a data a...
- Patent number 9,367,464
- Issue date Jun 14, 2016
- Intel Corporation
- Larisa Novakovsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Reduced power mode of a cache unit
- Patent number 9,360,924
- Issue date Jun 7, 2016
- Intel Corporation
- Alexander Gendler
- Y02 - TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMA...
Information Patent Grant
Multi latency configurable cache
- Patent number 8,996,833
- Issue date Mar 31, 2015
- Intel Corporation
- Larisa Novakovsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and apparatus for error correction in a cache
- Patent number 8,990,512
- Issue date Mar 24, 2015
- Intel Corporation
- Stanislav Shwartsman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Posting weakly ordered transactions
- Patent number 8,347,035
- Issue date Jan 1, 2013
- Intel Corporation
- Geeyarpuram N. Santhanakrishnan
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device, system and method of managing a resource request
- Patent number 7,958,510
- Issue date Jun 7, 2011
- Intel Corporation
- Abraham Mendelson
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
APPARATUS AND METHOD TO IDENTIFY THE SOURCE OF AN INTERRUPT
- Publication number 20230401061
- Publication date Dec 14, 2023
- Ashok RAJ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HARDWARE AND CONFIGURATION SUPPORT FOR ALLOCATING SHARED RESOURCES
- Publication number 20230325241
- Publication date Oct 12, 2023
- Intel Corporation
- Andrew J. HERDRICH
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC INCLUSIVE AND NON-INCLUSIVE CACHING POLICY
- Publication number 20230315630
- Publication date Oct 5, 2023
- Intel Corporation
- Hanna Alam
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD TO IDENTIFY THE SOURCE OF AN INTERRUPT
- Publication number 20210357221
- Publication date Nov 18, 2021
- Ashok RAJ
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Core-Only System Management Interrupt
- Publication number 20200349312
- Publication date Nov 5, 2020
- Intel Corporation
- Tsvika Kurts
- G01 - MEASURING TESTING
Information Patent Application
System, Apparatus And Method For Probeless Field Scan Of A Processor
- Publication number 20200096569
- Publication date Mar 26, 2020
- Intel Corporation
- Michael Mishaeli
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SUPPORTING HANG DETECTION AND DATA RECOVERY IN MICROPROCESSOR SYSTEMS
- Publication number 20190243701
- Publication date Aug 8, 2019
- Intel Corporation
- Tsvika Kurts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE BEHAVIOR FOR SECURE MEMORY REPARTITIONING SYSTEMS
- Publication number 20190102324
- Publication date Apr 4, 2019
- Intel Corporation
- Meltem Ozsoy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Core-Only System Management Interrupt
- Publication number 20190005160
- Publication date Jan 3, 2019
- Tsvika Kurts
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMUNICATING VIA A MAILBOX INTERFACE OF A PROCESSOR
- Publication number 20180181401
- Publication date Jun 28, 2018
- Intel Corporation
- Alexander Gendler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS FOR ENHANCING BIOS PERFORMANCE BY ALLEVIATING C...
- Publication number 20180095883
- Publication date Apr 5, 2018
- Intel Corporation
- Leon Polishuk
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Pipelined Prefetcher for Parallel Advancement Of Multiple Data Streams
- Publication number 20170286304
- Publication date Oct 5, 2017
- Intel Corporation
- Leeor Peled
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MASKING A POWER STATE OF A CORE OF A PROCESSOR
- Publication number 20170031412
- Publication date Feb 2, 2017
- Intel Corporation
- Alexander Gendler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Adaptive Hierarchical Cache Policy In A Microprocessor
- Publication number 20160342515
- Publication date Nov 24, 2016
- Intel Corporation
- Larisa Novakovsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Instruction and Logic for Speculative Request Support for Prefetching
- Publication number 20160283232
- Publication date Sep 29, 2016
- Raanan Sade
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMUNICATING VIA A MAILBOX INTERFACE OF A PROCESSOR
- Publication number 20160224098
- Publication date Aug 4, 2016
- ALEXANDER GENDLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Apparatus and Method to Transfer Data Packets between Domains of a...
- Publication number 20160092357
- Publication date Mar 31, 2016
- Shani Rehana
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD AND APPARATUS FOR CACHE LINE WRITE BACK OPERATION
- Publication number 20150178202
- Publication date Jun 25, 2015
- Rajesh M. Sankaran
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Restricting Clock Signal Delivery In A Processor
- Publication number 20140380081
- Publication date Dec 25, 2014
- Alexander Gendler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REDUCED POWER MODE OF A CACHE UNIT
- Publication number 20140359330
- Publication date Dec 4, 2014
- ALEXANDER GENDLER
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR IMPLEMENT A MULTI-LEVEL MEMORY HIERARCHY
- Publication number 20140298140
- Publication date Oct 2, 2014
- Theodros Yigzaw
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADAPTIVE HIERARCHICAL CACHE POLICY IN A MICROPROCESSOR
- Publication number 20140281239
- Publication date Sep 18, 2014
- Intel Corporation
- Larisa Novakovsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MULTI LATENCY CONFIGURABLE CACHE
- Publication number 20140258618
- Publication date Sep 11, 2014
- Larisa Novakovsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR MEMORY-HIERARCHY AWARE PRODUCER-CONSUMER I...
- Publication number 20140208031
- Publication date Jul 24, 2014
- Shlomo Raikin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE CIRCUIT HAVING A TAG ARRAY WITH SMALLER LATENCY THAN A DATA A...
- Publication number 20140208035
- Publication date Jul 24, 2014
- Larisa Novakovsky
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR MEMORY-HIERARCHY AWARE PRODUCER-CONSUMER I...
- Publication number 20140192069
- Publication date Jul 10, 2014
- Shlomo Raikin
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method And Apparatus For Error Correction In A Cache
- Publication number 20140122811
- Publication date May 1, 2014
- Stanislav Shwartsman
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
CACHE MEMORY STAGED REOPEN
- Publication number 20130318292
- Publication date Nov 28, 2013
- Iris Sorani
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS AND METHOD FOR DYNAMICALLY MANAGING MEMORY ACCESS BANDWID...
- Publication number 20130262826
- Publication date Oct 3, 2013
- Alexander Gendler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
POSTING WEAKLY ORDERED TRANSACTIONS
- Publication number 20100161907
- Publication date Jun 24, 2010
- Geeyarpuram N. Santhanakrishnan
- G06 - COMPUTING CALCULATING COUNTING

Larisa Novakovsky

Person

Patents Grantslast 30 patents

Apparatus and method to identify the source of an interrupt

Apparatus and method to identify the source of an interrupt

Apparatus and method to identify the source of an interrupt

System, apparatus and method for probeless field scan of a processor

Supporting hang detection and data recovery in microprocessor systems

Communicating via a mailbox interface of a processor

Core-only system management interrupt

Systems and methods for enhancing BIOS performance by alleviating c...

Pipelined prefetcher for parallel advancement of multiple data streams

Apparatus and method for memory-hierarchy aware producer-consumer i...

Cache memory staged reopen

Masking a power state of a core of a processor

Adaptive hierarchical cache policy in a microprocessor

Apparatus and method to transfer data packets between domains of a...

Restricting clock signal delivery in a processor

Method and apparatus for cache line write back operation

Apparatus and method for implement a multi-level memory hierarchy

Adaptive hierarchical cache policy in a microprocessor

Cache circuit having a tag array with smaller latency than a data a...

Reduced power mode of a cache unit

Multi latency configurable cache

Method and apparatus for error correction in a cache

Posting weakly ordered transactions

Device, system and method of managing a resource request

Patents Applicationslast 30 patents

APPARATUS AND METHOD TO IDENTIFY THE SOURCE OF AN INTERRUPT

HARDWARE AND CONFIGURATION SUPPORT FOR ALLOCATING SHARED RESOURCES

DYNAMIC INCLUSIVE AND NON-INCLUSIVE CACHING POLICY

APPARATUS AND METHOD TO IDENTIFY THE SOURCE OF AN INTERRUPT

Core-Only System Management Interrupt

System, Apparatus And Method For Probeless Field Scan Of A Processor

SUPPORTING HANG DETECTION AND DATA RECOVERY IN MICROPROCESSOR SYSTEMS

CACHE BEHAVIOR FOR SECURE MEMORY REPARTITIONING SYSTEMS

Core-Only System Management Interrupt

COMMUNICATING VIA A MAILBOX INTERFACE OF A PROCESSOR

SYSTEMS AND METHODS FOR ENHANCING BIOS PERFORMANCE BY ALLEVIATING C...

Pipelined Prefetcher for Parallel Advancement Of Multiple Data Streams

MASKING A POWER STATE OF A CORE OF A PROCESSOR

Adaptive Hierarchical Cache Policy In A Microprocessor

Instruction and Logic for Speculative Request Support for Prefetching

COMMUNICATING VIA A MAILBOX INTERFACE OF A PROCESSOR

Apparatus and Method to Transfer Data Packets between Domains of a...

METHOD AND APPARATUS FOR CACHE LINE WRITE BACK OPERATION

Restricting Clock Signal Delivery In A Processor

REDUCED POWER MODE OF A CACHE UNIT

APPARATUS AND METHOD FOR IMPLEMENT A MULTI-LEVEL MEMORY HIERARCHY

ADAPTIVE HIERARCHICAL CACHE POLICY IN A MICROPROCESSOR

MULTI LATENCY CONFIGURABLE CACHE

APPARATUS AND METHOD FOR MEMORY-HIERARCHY AWARE PRODUCER-CONSUMER I...

CACHE CIRCUIT HAVING A TAG ARRAY WITH SMALLER LATENCY THAN A DATA A...

APPARATUS AND METHOD FOR MEMORY-HIERARCHY AWARE PRODUCER-CONSUMER I...

Method And Apparatus For Error Correction In A Cache

CACHE MEMORY STAGED REOPEN

APPARATUS AND METHOD FOR DYNAMICALLY MANAGING MEMORY ACCESS BANDWID...

POSTING WEAKLY ORDERED TRANSACTIONS