Larry R. Fenstermaker

Person

Nazareth, PA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Distributed front-end FIFO for source-synchronous interfaces with n...
- Patent number 7,808,855
- Issue date Oct 5, 2010
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Distributed front-end FIFO for source-synchronized interfaces with...
- Patent number 7,573,770
- Issue date Aug 11, 2009
- Lattice Semiconductor Corporation
- Fulong Zhang
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic over-voltage protection scheme for interface circuitry
- Patent number 7,547,995
- Issue date Jun 16, 2009
- Lattice Semiconductor Corporation
- William B. Andrews
- Y10 - TECHNICAL SUBJECTS COVERED BY FORMER USPC
Information Patent Grant
Low static current drain logic circuit
- Patent number 7,429,875
- Issue date Sep 30, 2008
- Lattice Semiconductor Corporation
- Larry R. Fenstermaker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bitline twisting scheme for multiport memory
- Patent number 7,414,913
- Issue date Aug 19, 2008
- Lattice Semiconductor Corporation
- Larry Fenstermaker
- G11 - INFORMATION STORAGE
Information Patent Grant
Clock reset address decoder for block memory
- Patent number 7,263,024
- Issue date Aug 28, 2007
- Lattice Semiconductor Corporation
- Larry R. Fenstermaker
- G11 - INFORMATION STORAGE
Information Patent Grant
Pseudo-dynamic word-line driver
- Patent number 7,242,634
- Issue date Jul 10, 2007
- Lattice Semiconductor Corporation
- Larry R. Fenstermaker
- G11 - INFORMATION STORAGE
Information Patent Grant
Dynamic over-voltage protection scheme for integrated-circuit devices
- Patent number 7,230,810
- Issue date Jun 12, 2007
- Lattice Semiconductor Corporation
- William B. Andrews
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interface circuitry for electrical systems
- Patent number 7,215,149
- Issue date May 8, 2007
- Lattice Semiconductor Corporation
- William B. Andrews
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Address isolation for user-defined configuration memory in programm...
- Patent number 7,196,963
- Issue date Mar 27, 2007
- Lattice Semiconductor Corporation
- Larry R. Fenstermaker
- G11 - INFORMATION STORAGE
Information Patent Grant
Low power asynchronous sense amp
- Patent number 7,161,862
- Issue date Jan 9, 2007
- Lattice Semiconductor Corporation
- Mou C. Lin
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic device having a configurable DRAM with transpare...
- Patent number 7,129,749
- Issue date Oct 31, 2006
- Lattice Semiconductor Corporation
- Larry R. Fenstermaker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Programmable logic devices with integrated standard-cell logic blocks
- Patent number 6,975,137
- Issue date Dec 13, 2005
- Lattice Semiconductor Corporation
- John A. Schadt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Bi-directional buffering for memory data lines
- Patent number 6,882,555
- Issue date Apr 19, 2005
- Lattice Semiconductor Corporation
- Larry R. Fenstermaker
- G11 - INFORMATION STORAGE
Information Patent Grant
Programmable logic devices with integrated standard-cell logic blocks
- Patent number 6,870,395
- Issue date Mar 22, 2005
- Lattice Semiconductor Corporation
- John A. Schadt
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method and system for testing multiport memories
- Patent number 6,216,241
- Issue date Apr 10, 2001
- Agere Systems Guardian Corp.
- Larry Ray Fenstermaker
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for built-in self-testing of ring-address FIFOs having a dat...
- Patent number 5,978,935
- Issue date Nov 2, 1999
- Ilyoung Kim
- G11 - INFORMATION STORAGE
Information Patent Grant
Fifo with word line match circuits for flag generation
- Patent number 5,345,419
- Issue date Sep 6, 1994
- AT&T Bell Laboratories
- Larry R. Fenstermaker
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Low static current drain logic circuit
- Publication number 20080143380
- Publication date Jun 19, 2008
- Larry R. Fenstermaker
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Application
PSEUDO-DYNAMIC WORD-LINE DRIVER
- Publication number 20070121415
- Publication date May 31, 2007
- Larry R. Fenstermaker
- G11 - INFORMATION STORAGE
Information Patent Application
Clock reset address decoder for block memory
- Publication number 20070086263
- Publication date Apr 19, 2007
- Larry R. Fenstermaker
- G11 - INFORMATION STORAGE
Information Patent Application
Bi-directional buffering for memory data lines
- Publication number 20040257860
- Publication date Dec 23, 2004
- Lattice Semiconductor Corporation
- Larry R. Fenstermaker
- G11 - INFORMATION STORAGE
Information Patent Application
Programmable logic devices with integrated standard-cell logic blocks
- Publication number 20040183564
- Publication date Sep 23, 2004
- Lattice Semiconductor Corporation, a Delaware corporation
- John A. Schadt
- H03 - BASIC ELECTRONIC CIRCUITRY

Larry R. Fenstermaker

Person

Patents Grantslast 30 patents

Distributed front-end FIFO for source-synchronous interfaces with n...

Distributed front-end FIFO for source-synchronized interfaces with...

Dynamic over-voltage protection scheme for interface circuitry

Low static current drain logic circuit

Bitline twisting scheme for multiport memory

Clock reset address decoder for block memory

Pseudo-dynamic word-line driver

Dynamic over-voltage protection scheme for integrated-circuit devices

Interface circuitry for electrical systems

Address isolation for user-defined configuration memory in programm...

Low power asynchronous sense amp

Programmable logic device having a configurable DRAM with transpare...

Programmable logic devices with integrated standard-cell logic blocks

Bi-directional buffering for memory data lines

Programmable logic devices with integrated standard-cell logic blocks

Method and system for testing multiport memories

Method for built-in self-testing of ring-address FIFOs having a dat...

Fifo with word line match circuits for flag generation

Patents Applicationslast 30 patents

Low static current drain logic circuit

PSEUDO-DYNAMIC WORD-LINE DRIVER

Clock reset address decoder for block memory

Bi-directional buffering for memory data lines

Programmable logic devices with integrated standard-cell logic blocks