Lars W. Liebmann

Person

Poughquag, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Self aligned buried power rail
- Patent number 12,142,516
- Issue date Nov 12, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Nicholas V. Licausi
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metallization lines on integrated circuit products
- Patent number 12,131,994
- Issue date Oct 29, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High density logic formation using multi-dimensional laser annealing
- Patent number 12,087,640
- Issue date Sep 10, 2024
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated high efficiency transistor cooling
- Patent number 12,051,638
- Issue date Jul 30, 2024
- Tokyo Electron Limited
- Daniel Chanemougame
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power delivery network for CFET with buried power rails
- Patent number 12,040,271
- Issue date Jul 16, 2024
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for threshold voltage tuning through selective deposition of...
- Patent number 12,020,990
- Issue date Jun 25, 2024
- Tokyo Electron Limited
- Jeffrey Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of manufacturing a semiconductor apparatus having stacked de...
- Patent number 12,014,984
- Issue date Jun 18, 2024
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Inter-level handshake for dense 3D logic integration
- Patent number 12,002,862
- Issue date Jun 4, 2024
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate contact structures and cross-coupled contact structures for tr...
- Patent number 12,002,869
- Issue date Jun 4, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power-tap pass-through to connect a buried power rail to front-side...
- Patent number 11,961,802
- Issue date Apr 16, 2024
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Double cross-couple for two-row flip-flop using CFET
- Patent number 11,923,364
- Issue date Mar 5, 2024
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Architecture design and process for manufacturing monolithically in...
- Patent number 11,901,360
- Issue date Feb 13, 2024
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multi-tier backside power delivery network for dense gate-on-gate 3...
- Patent number 11,830,852
- Issue date Nov 28, 2023
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Monolithic formation of a set of interconnects below active devices
- Patent number 11,791,271
- Issue date Oct 17, 2023
- Tokyo Electron Limited
- Daniel Chanemougame
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Metallization lines on integrated circuit products
- Patent number 11,791,263
- Issue date Oct 17, 2023
- GLOBALFOUNDRIES U.S. INC.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of 3D logic fabrication to sequentially decrease processing...
- Patent number 11,764,113
- Issue date Sep 19, 2023
- Tokyo Electron Limited
- Jeffrey Smith
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional semiconductor device
- Patent number 11,764,266
- Issue date Sep 19, 2023
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power delivery network for CFET with buried power rails
- Patent number 11,735,525
- Issue date Aug 22, 2023
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Three-dimensional memory cell structure
- Patent number 11,723,187
- Issue date Aug 8, 2023
- Tokyo Electron Limited
- Paul Gutwin
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for automated standard cell design
- Patent number 11,714,945
- Issue date Aug 1, 2023
- Tokyo Electron Limited
- Lars Liebmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Coaxial contacts for 3D logic and memory
- Patent number 11,676,968
- Issue date Jun 13, 2023
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CFET SRAM bit cell with two stacked device decks
- Patent number 11,665,878
- Issue date May 30, 2023
- Tokyo Electron Limited
- Daniel Chanemougame
- G11 - INFORMATION STORAGE
Information Patent Grant
Connections from buried interconnects to device terminals in multip...
- Patent number 11,646,318
- Issue date May 9, 2023
- Tokyo Electron Limited
- Daniel Chanemougame
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
3D complementary metal oxide semiconductor (CMOS) device and method...
- Patent number 11,631,671
- Issue date Apr 18, 2023
- Tokyo Electron Limited
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Gate contact structure for a transistor device
- Patent number 11,621,333
- Issue date Apr 4, 2023
- GLOBALFOUNDRIES U.S. INC.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Power distribution network for 3D logic and memory
- Patent number 11,616,020
- Issue date Mar 28, 2023
- Tokyo Electron Limited
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated high efficiency gate on gate cooling
- Patent number 11,581,242
- Issue date Feb 14, 2023
- Tokyo Electron Limited
- Daniel Chanemougame
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Apparatus and method for simultaneous formation of diffusion break,...
- Patent number 11,574,845
- Issue date Feb 7, 2023
- Tokyo Electron Limited
- Daniel Chanemougame
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for automated standard cell design
- Patent number 11,550,985
- Issue date Jan 10, 2023
- Tokyo Electron Limited
- Lars Liebmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
CFET SRAM bit cell with three stacked device decks
- Patent number 11,545,497
- Issue date Jan 3, 2023
- Tokyo Electron Limited
- Daniel Chanemougame
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS
- Publication number 20240413082
- Publication date Dec 12, 2024
- GLOBALFOUNDRIES U.S. Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED HIGH EFFICIENCY TRANSISTOR COOLING
- Publication number 20240347422
- Publication date Oct 17, 2024
- TOKYO ELECTRON LIMITED
- Daniel CHANEMOUGAME
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED BACKBONE FOR FORKSHEET TRANSISTORS
- Publication number 20240213250
- Publication date Jun 27, 2024
- Intel Corporation
- Shao Ming KOH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DIELECTRIC BARRIER FOR BACKSIDE INTERCONNECT SEPARATION
- Publication number 20240204064
- Publication date Jun 20, 2024
- Intel Corporation
- Guillaume Bouche
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
High Density Transistor and Routing Track Architecture
- Publication number 20240202415
- Publication date Jun 20, 2024
- Intel Corporation
- Quan Shi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTIVE DEPOSITION OF LINER AND BARRIER FILMS FOR RESISTANCE REDU...
- Publication number 20240047342
- Publication date Feb 8, 2024
- TOKYO ELECTRON LIMITED
- Jeffrey SMITH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
MONOLITHIC FORMATION OF A SET OF INTERCONNECTS BELOW ACTIVE DEVICES
- Publication number 20230411298
- Publication date Dec 21, 2023
- TOKYO ELECTRON LIMITED
- Daniel Chanemougame
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS
- Publication number 20230395502
- Publication date Dec 7, 2023
- GLOBALFOUNDRIES U.S. Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER DELIVERY NETWORK FOR CFET WITH BURIED POWER RAILS
- Publication number 20230326855
- Publication date Oct 12, 2023
- TOKYO ELECTRON LIMITED
- Lars LIEBMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method for Automated Standard Cell Design
- Publication number 20230325574
- Publication date Oct 12, 2023
- TOKYO ELECTRON LIMITED
- Lars Liebmann
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Wiring in Diffusion Breaks in an Integrated Circuit
- Publication number 20230223404
- Publication date Jul 13, 2023
- TOKYO ELECTRON LIMITED
- Lars LIEBMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CONNECTIONS FROM BURIED INTERCONNECTS TO DEVICE TERMINALS IN MULTIP...
- Publication number 20230207566
- Publication date Jun 29, 2023
- TOKYO ELECTRON LIMITED
- Daniel Chanemougame
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
- Publication number 20230100332
- Publication date Mar 30, 2023
- TOKYO ELECTRON LIMITED
- Lars LIEBMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
TAPERED DEVICE FOR LATERAL GATE ALL AROUND DEVICES
- Publication number 20230078381
- Publication date Mar 16, 2023
- TOKYO ELECTRON LIMITED
- Lars LIEBMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED METHOD FOR VERTICAL RECESS FOR 3D DEVICE INTEGRATION
- Publication number 20230036597
- Publication date Feb 2, 2023
- TOKYO ELECTRON LIMITED
- Jeffrey SMITH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Method of manufacturing a semiconductor apparatus having stacked de...
- Publication number 20230024975
- Publication date Jan 26, 2023
- TOKYO ELECTRON LIMITED
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INDEPENDENT GATE CONTACTS FOR CFET
- Publication number 20230017350
- Publication date Jan 19, 2023
- TOKYO ELECTRON LIMITED
- Daniel CHANEMOUGAME
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR STRUCTURE HAVING STACKED GATES AND METHOD OF MANUFACT...
- Publication number 20220416048
- Publication date Dec 29, 2022
- TOKYO ELECTRON LIMITED
- Jeffrey SMITH
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
GATE CONTACT STRUCTURES AND CROSS-COUPLED CONTACT STRUCTURES FOR TR...
- Publication number 20220416054
- Publication date Dec 29, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Ruilong Xie
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGHLY REGULAR LOGIC DESIGN FOR EFFICIENT 3D INTEGRATION
- Publication number 20220375921
- Publication date Nov 24, 2022
- TOKYO ELECTRON LIMITED
- Lars Liebmann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INVERTED CROSS-COUPLE FOR TOP-TIER FET FOR MULTI-TIER GATE-ON-GATE 3DI
- Publication number 20220367461
- Publication date Nov 17, 2022
- TOKYO ELECTRON LIMITED
- Daniel CHANEMOUGAME
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL MEMORY CELL STRUCTURE
- Publication number 20220302121
- Publication date Sep 22, 2022
- TOKYO ELECTRON LIMITED
- Paul GUTWIN
- G11 - INFORMATION STORAGE
Information Patent Application
HIGH DENSITY LOGIC FORMATION USING MULTI-DIMENSIONAL LASER ANNEALING
- Publication number 20220277957
- Publication date Sep 1, 2022
- TOKYO ELECTRON LIMITED
- H. Jim Fulford
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INVERTED TOP-TIER FET FOR MULTI-TIER GATE-ON-GATE 3-DIMENSION INTEG...
- Publication number 20220271033
- Publication date Aug 25, 2022
- Daniel CHANEMOUGAME
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED HIGH EFFICIENCY GATE ON GATE COOLING
- Publication number 20220223497
- Publication date Jul 14, 2022
- TOKYO ELECTRON LIMITED
- Daniel CHANEMOUGAME
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATED HIGH EFFICIENCY TRANSISTOR COOLING
- Publication number 20220223496
- Publication date Jul 14, 2022
- TOKYO ELECTRON LIMITED
- Daniel CHANEMOUGAME
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF ALIGNED BURIED POWER RAIL
- Publication number 20220181198
- Publication date Jun 9, 2022
- GLOBALFOUNDRIES U.S. Inc.
- Nicholas V. LICAUSI
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
POWER-TAP PASS-THROUGH TO CONNECT A BURIED POWER RAIL TO FRONT-SIDE...
- Publication number 20220181258
- Publication date Jun 9, 2022
- TOKYO ELECTRON LIMITED
- Lars LIEBMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
- Publication number 20220181441
- Publication date Jun 9, 2022
- TOKYO ELECTRON LIMITED
- Lars LIEBMANN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTER-TIER POWER DELIVERY NETWORK (PDN) FOR DENSE GATE-ON-GATE 3D L...
- Publication number 20220181263
- Publication date Jun 9, 2022
- Lars LIEBMANN
- H01 - BASIC ELECTRIC ELEMENTS

Lars W. Liebmann

Person

Patents Grantslast 30 patents

Self aligned buried power rail

Metallization lines on integrated circuit products

High density logic formation using multi-dimensional laser annealing

Integrated high efficiency transistor cooling

Power delivery network for CFET with buried power rails

Method for threshold voltage tuning through selective deposition of...

Method of manufacturing a semiconductor apparatus having stacked de...

Inter-level handshake for dense 3D logic integration

Gate contact structures and cross-coupled contact structures for tr...

Power-tap pass-through to connect a buried power rail to front-side...

Double cross-couple for two-row flip-flop using CFET

Architecture design and process for manufacturing monolithically in...

Multi-tier backside power delivery network for dense gate-on-gate 3...

Monolithic formation of a set of interconnects below active devices

Metallization lines on integrated circuit products

Method of 3D logic fabrication to sequentially decrease processing...

Three-dimensional semiconductor device

Power delivery network for CFET with buried power rails

Three-dimensional memory cell structure

Method for automated standard cell design

Coaxial contacts for 3D logic and memory

CFET SRAM bit cell with two stacked device decks

Connections from buried interconnects to device terminals in multip...

3D complementary metal oxide semiconductor (CMOS) device and method...

Gate contact structure for a transistor device

Power distribution network for 3D logic and memory

Integrated high efficiency gate on gate cooling

Apparatus and method for simultaneous formation of diffusion break,...

Method for automated standard cell design

CFET SRAM bit cell with three stacked device decks

Patents Applicationslast 30 patents

METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS

INTEGRATED HIGH EFFICIENCY TRANSISTOR COOLING

SELF-ALIGNED BACKBONE FOR FORKSHEET TRANSISTORS

DIELECTRIC BARRIER FOR BACKSIDE INTERCONNECT SEPARATION

High Density Transistor and Routing Track Architecture

SELECTIVE DEPOSITION OF LINER AND BARRIER FILMS FOR RESISTANCE REDU...

MONOLITHIC FORMATION OF A SET OF INTERCONNECTS BELOW ACTIVE DEVICES

METALLIZATION LINES ON INTEGRATED CIRCUIT PRODUCTS

POWER DELIVERY NETWORK FOR CFET WITH BURIED POWER RAILS

Method for Automated Standard Cell Design

Wiring in Diffusion Breaks in an Integrated Circuit

CONNECTIONS FROM BURIED INTERCONNECTS TO DEVICE TERMINALS IN MULTIP...

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

TAPERED DEVICE FOR LATERAL GATE ALL AROUND DEVICES

SELF-ALIGNED METHOD FOR VERTICAL RECESS FOR 3D DEVICE INTEGRATION

Method of manufacturing a semiconductor apparatus having stacked de...

INDEPENDENT GATE CONTACTS FOR CFET

SEMICONDUCTOR STRUCTURE HAVING STACKED GATES AND METHOD OF MANUFACT...

GATE CONTACT STRUCTURES AND CROSS-COUPLED CONTACT STRUCTURES FOR TR...

HIGHLY REGULAR LOGIC DESIGN FOR EFFICIENT 3D INTEGRATION

INVERTED CROSS-COUPLE FOR TOP-TIER FET FOR MULTI-TIER GATE-ON-GATE 3DI

THREE-DIMENSIONAL MEMORY CELL STRUCTURE

HIGH DENSITY LOGIC FORMATION USING MULTI-DIMENSIONAL LASER ANNEALING

INVERTED TOP-TIER FET FOR MULTI-TIER GATE-ON-GATE 3-DIMENSION INTEG...

INTEGRATED HIGH EFFICIENCY GATE ON GATE COOLING

INTEGRATED HIGH EFFICIENCY TRANSISTOR COOLING

SELF ALIGNED BURIED POWER RAIL

POWER-TAP PASS-THROUGH TO CONNECT A BURIED POWER RAIL TO FRONT-SIDE...

THREE-DIMENSIONAL SEMICONDUCTOR DEVICE

INTER-TIER POWER DELIVERY NETWORK (PDN) FOR DENSE GATE-ON-GATE 3D L...