Laura R. Darden

Person

Essex Junction, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Cell placement in a circuit with shared inputs and outputs
- Patent number 10,755,017
- Issue date Aug 25, 2020
- International Business Machines Corporation
- Brent A. Anderson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Hierarchical trim management for self-aligned double patterning
- Patent number 10,586,009
- Issue date Mar 10, 2020
- International Business Machines Corporation
- Laura R. Darden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Methods for design rule checking with abstracted via obstructions
- Patent number 7,725,850
- Issue date May 25, 2010
- International Business Machines Corporation
- Laura R. Darden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Overlapping shape design rule error prevention
- Patent number 7,278,127
- Issue date Oct 2, 2007
- International Business Machines Corporation
- Laura R. Darden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Spacing violation checker
- Patent number 6,779,165
- Issue date Aug 17, 2004
- International Business Machines Corporation
- Laura R. Darden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method and system of modifying integrated circuit power rails
- Patent number 6,598,206
- Issue date Jul 22, 2003
- International Business Machines Corporation
- Laura R. Darden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Spacing violation checker
- Patent number 6,301,689
- Issue date Oct 9, 2001
- International Business Machines Corporation
- Laura R. Darden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Three dimensional track-based parasitic extraction
- Patent number 6,185,722
- Issue date Feb 6, 2001
- International Business Machines Corporation
- Laura Rohwedder Darden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Redundant vias
- Patent number 6,026,224
- Issue date Feb 15, 2000
- International Business Machines Corporation
- Laura Rohwedder Darden
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
CELL PLACEMENT IN A CIRCUIT WITH SHARED INPUTS AND OUTPUTS
- Publication number 20200019665
- Publication date Jan 16, 2020
- International Business Machines Corporation
- BRENT A. ANDERSON
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
HIERARCHICAL TRIM MANAGEMENT FOR SELF-ALIGNED DOUBLE PATTERNING
- Publication number 20190179994
- Publication date Jun 13, 2019
- International Business Machines Corporation
- Laura R. Darden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS FOR DESIGN RULE CHECKING WITH ABSTRACTED VIA OBSTRUCTIONS
- Publication number 20090037857
- Publication date Feb 5, 2009
- International Business Machines Corporation
- Laura R. Darden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OVERLAPPING SHAPE DESIGN RULE ERROR PREVENTION
- Publication number 20060036986
- Publication date Feb 16, 2006
- International Business Machines Corporation
- Laura R. Darden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method and system of modifying integrated circuit power rails
- Publication number 20020170020
- Publication date Nov 14, 2002
- International Business Machines Corporation
- Laura R. Darden
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Spacing violation checker
- Publication number 20010042236
- Publication date Nov 15, 2001
- Laura R. Darden
- G06 - COMPUTING CALCULATING COUNTING

Laura R. Darden

Person

Patents Grantslast 30 patents

Cell placement in a circuit with shared inputs and outputs

Hierarchical trim management for self-aligned double patterning

Methods for design rule checking with abstracted via obstructions

Overlapping shape design rule error prevention

Spacing violation checker

Method and system of modifying integrated circuit power rails

Spacing violation checker

Three dimensional track-based parasitic extraction

Redundant vias

Patents Applicationslast 30 patents

CELL PLACEMENT IN A CIRCUIT WITH SHARED INPUTS AND OUTPUTS

HIERARCHICAL TRIM MANAGEMENT FOR SELF-ALIGNED DOUBLE PATTERNING

METHODS FOR DESIGN RULE CHECKING WITH ABSTRACTED VIA OBSTRUCTIONS

OVERLAPPING SHAPE DESIGN RULE ERROR PREVENTION

Method and system of modifying integrated circuit power rails

Spacing violation checker