Laura S. Chadwick

Person

Essex Junction, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Integrated circuit (IC) design analysis and feature extraction
- Patent number 9,754,071
- Issue date Sep 5, 2017
- GLOBALFOUNDRIES Inc.
- Haraprasad Nanjundappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of laying out integrated circuit design based on known polys...
- Patent number 7,890,906
- Issue date Feb 15, 2011
- International Business Machines Corporation
- Laura S. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
System and method to optimize semiconductor power by integration of...
- Patent number 7,877,714
- Issue date Jan 25, 2011
- International Business Machines Corporation
- Theodoros E. Anemikos
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit with uniform polysilicon perimeter density, meth...
- Patent number 7,849,433
- Issue date Dec 7, 2010
- International Business Machines Corporation
- Laura S. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of optimizing power usage of an integrated circuit design by...
- Patent number 7,810,054
- Issue date Oct 5, 2010
- International Business Machines Corporation
- Theodoros E. Anemikos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IC chip design modeling using perimeter density to electrical chara...
- Patent number 7,805,693
- Issue date Sep 28, 2010
- International Business Machines Corporation
- Laura S. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Design structure for monitoring cross chip delay variation on a sem...
- Patent number 7,487,487
- Issue date Feb 3, 2009
- International Business Machines Corporation
- Anthony D. Polson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for testing embedded DRAM arrays
- Patent number 7,237,165
- Issue date Jun 26, 2007
- International Business Machines Corporation
- Laura S. Chadwick
- G11 - INFORMATION STORAGE
Information Patent Grant
Method for testing embedded DRAM arrays
- Patent number 7,073,100
- Issue date Jul 4, 2006
- International Business Machines Corporation
- Laura S. Chadwick
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
INTEGRATED CIRCUIT (IC) DESIGN ANALYSIS AND FEATURE EXTRACTION
- Publication number 20170242952
- Publication date Aug 24, 2017
- GLOBALFOUNDRIES INC.
- Haraprasad Nanjundappa
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD OF LAYING OUT INTEGRATED CIRCUIT DESIGN BASED ON KNOWN POLYS...
- Publication number 20090282380
- Publication date Nov 12, 2009
- Laura S. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT WITH UNIFORM POLYSILICON PERIMETER DENSITY, METH...
- Publication number 20090278222
- Publication date Nov 12, 2009
- Laura S. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD TO OPTIMIZE POWER BY TUNING THE SELECTIVE VOLTAGE BINNING CU...
- Publication number 20090228843
- Publication date Sep 10, 2009
- International Business Machines Corporation
- Theodoros E. Anemikos
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEM AND METHOD TO OPTIMIZE SEMICONDUCTOR POWER BY INTEGRATION OF...
- Publication number 20090217221
- Publication date Aug 27, 2009
- International Business Machines Corporation
- Theodoros E. ANEMIKOS
- G01 - MEASURING TESTING
Information Patent Application
IC CHIP DESIGN MODELING USING PERIMETER DENSITY TO ELECTRICAL CHARA...
- Publication number 20090210834
- Publication date Aug 20, 2009
- Laura S. Chadwick
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Method for testing embedded DRAM arrays
- Publication number 20050088888
- Publication date Apr 28, 2005
- Laura S. Chadwick
- G11 - INFORMATION STORAGE
Information Patent Application
Method for testing embedded DRAM arrays
- Publication number 20040093539
- Publication date May 13, 2004
- International Business Machines Corporation
- Laura S. Chadwick
- G11 - INFORMATION STORAGE

Laura S. Chadwick

Person

Patents Grantslast 30 patents

Integrated circuit (IC) design analysis and feature extraction

Method of laying out integrated circuit design based on known polys...

System and method to optimize semiconductor power by integration of...

Integrated circuit with uniform polysilicon perimeter density, meth...

Method of optimizing power usage of an integrated circuit design by...

IC chip design modeling using perimeter density to electrical chara...

Design structure for monitoring cross chip delay variation on a sem...

Method for testing embedded DRAM arrays

Method for testing embedded DRAM arrays

Patents Applicationslast 30 patents

INTEGRATED CIRCUIT (IC) DESIGN ANALYSIS AND FEATURE EXTRACTION

METHOD OF LAYING OUT INTEGRATED CIRCUIT DESIGN BASED ON KNOWN POLYS...

INTEGRATED CIRCUIT WITH UNIFORM POLYSILICON PERIMETER DENSITY, METH...

METHOD TO OPTIMIZE POWER BY TUNING THE SELECTIVE VOLTAGE BINNING CU...

SYSTEM AND METHOD TO OPTIMIZE SEMICONDUCTOR POWER BY INTEGRATION OF...

IC CHIP DESIGN MODELING USING PERIMETER DENSITY TO ELECTRICAL CHARA...

Method for testing embedded DRAM arrays

Method for testing embedded DRAM arrays