Laurent F. Stadler

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San Francisco, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
Dual clock interface for an integrated circuit
- Patent number 7,725,754
- Issue date May 25, 2010
- Xilinx, Inc.
- Laurent Fabris Stadler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface device lane configuration
- Patent number 7,702,840
- Issue date Apr 20, 2010
- Xilinx, Inc.
- Patrick C. McCarthy
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Configurable interface
- Patent number 7,626,418
- Issue date Dec 1, 2009
- Xilinx, Inc.
- Paige A. Kolze
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Hard macro-to-user logic interface
- Patent number 7,573,295
- Issue date Aug 11, 2009
- Xilinx, Inc.
- Laurent F. Stadler
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for bus mastering for devices resident in configurable syste...
- Patent number 7,107,374
- Issue date Sep 12, 2006
- Xilinx, Inc.
- Laurent Stadler
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for delivering packet boundary or other metadata to and from...
- Patent number 6,889,266
- Issue date May 3, 2005
- Xilinx, Inc.
- Laurent Stadler
- G06 - COMPUTING CALCULATING COUNTING