Laurent Isenegger

Person

Morgan Hill, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Write request buffer capable of responding to read requests
- Patent number 12,254,213
- Issue date Mar 18, 2025
- Micron Technology, Inc.
- Nikesh Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Request control for memory sub-systems
- Patent number 12,182,442
- Issue date Dec 31, 2024
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Command scheduling component for memory
- Patent number 12,112,786
- Issue date Oct 8, 2024
- Micron Technology, Inc.
- Patrick A. La Fratta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interleaved cache prefetching
- Patent number 11,886,348
- Issue date Jan 30, 2024
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Write request thresholding
- Patent number 11,854,600
- Issue date Dec 26, 2023
- Micron Technology, Inc.
- Nikesh Agarwal
- G11 - INFORMATION STORAGE
Information Patent Grant
Using a second content-addressable memory to manage memory burst ac...
- Patent number 11,847,058
- Issue date Dec 19, 2023
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Memory-flow control register
- Patent number 11,836,096
- Issue date Dec 5, 2023
- Micron Technology, Inc.
- Nikesh Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Outstanding transaction monitoring for memory sub-systems
- Patent number 11,809,710
- Issue date Nov 7, 2023
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Dynamic queue depth adjustment
- Patent number 11,782,851
- Issue date Oct 10, 2023
- Micron Technology, Inc.
- Robert M. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Direct memory access (DMA) commands for noncontiguous source and de...
- Patent number 11,604,749
- Issue date Mar 14, 2023
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interleaved cache prefetching
- Patent number 11,599,472
- Issue date Mar 7, 2023
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Request control for memory sub-systems
- Patent number 11,593,024
- Issue date Feb 28, 2023
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quality of service levels for a direct memory access engine in a me...
- Patent number 11,461,256
- Issue date Oct 4, 2022
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using a second content-addressable memory to manage memory burst ac...
- Patent number 11,442,867
- Issue date Sep 13, 2022
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing processing of memory commands in a memory subsystem with a...
- Patent number 11,301,383
- Issue date Apr 12, 2022
- Micron Technology, Inc.
- Patrick A. La Fratta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Managing memory commands in a memory subsystem by adjusting a maxim...
- Patent number 11,175,859
- Issue date Nov 16, 2021
- Micron Technology, Inc.
- Patrick A. La Fratta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Direct memory access (DMA) commands for noncontiguous source and de...
- Patent number 11,086,808
- Issue date Aug 10, 2021
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Quality of service levels for a direct memory access engine in a me...
- Patent number 10,990,548
- Issue date Apr 27, 2021
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
COMMAND SCHEDULING COMPONENT FOR MEMORY
- Publication number 20250014628
- Publication date Jan 9, 2025
- Micron Technology, Inc.
- Patrick A. La Fratta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REQUEST CONTROL FOR MEMORY SUB-SYSTEMS
- Publication number 20230214155
- Publication date Jul 6, 2023
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERLEAVED CACHE PREFETCHING
- Publication number 20230205701
- Publication date Jun 29, 2023
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Write Request Buffer
- Publication number 20230195368
- Publication date Jun 22, 2023
- Micron Technology, Inc.
- Nikesh Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Memory-Flow Control Register
- Publication number 20230195659
- Publication date Jun 22, 2023
- Micron Technology, Inc.
- Nikesh Agarwal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
OUTSTANDING TRANSACTION MONITORING FOR MEMORY SUB-SYSTEMS
- Publication number 20230098454
- Publication date Mar 30, 2023
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERLEAVED CACHE PREFETCHING
- Publication number 20230063747
- Publication date Mar 2, 2023
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
REQUEST CONTROL FOR MEMORY SUB-SYSTEMS
- Publication number 20230067576
- Publication date Mar 2, 2023
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WRITE REQUEST THRESHOLDING
- Publication number 20230062167
- Publication date Mar 2, 2023
- Micron Technology, Inc.
- Nikesh Agarwal
- G11 - INFORMATION STORAGE
Information Patent Application
COMMAND RETRIEVAL AND ISSUANCE POLICY
- Publication number 20230065395
- Publication date Mar 2, 2023
- Micron Technology, Inc.
- Robert M. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
COMMAND SCHEDULING COMPONENT FOR MEMORY
- Publication number 20230060826
- Publication date Mar 2, 2023
- Micron Technology, Inc.
- Patrick A. La Fratta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DYNAMIC QUEUE DEPTH ADJUSTMENT
- Publication number 20230060874
- Publication date Mar 2, 2023
- Micron Technology, Inc.
- Robert M. Walker
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING A SECOND CONTENT-ADDRESSABLE MEMORY TO MANAGE MEMORY BURST AC...
- Publication number 20220382677
- Publication date Dec 1, 2022
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
MANAGING PROCESSING OF MEMORY COMMANDS IN A MEMORY SUBSYSTEM WITH A...
- Publication number 20220019533
- Publication date Jan 20, 2022
- Micron Technology, Inc.
- Patrick A. La Fratta
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECT MEMORY ACCESS (DMA) COMMANDS FOR NONCONTIGUOUS SOURCE AND DE...
- Publication number 20210365395
- Publication date Nov 25, 2021
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
QUALITY OF SERVICE LEVELS FOR A DIRECT MEMORY ACCESS ENGINE IN A ME...
- Publication number 20210232517
- Publication date Jul 29, 2021
- Micron Technology, Inc.
- Dhawal Bavishi
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
DIRECT MEMORY ACCESS (DMA) COMMANDS FOR NONCONTIGUOUS SOURCE AND DE...
- Publication number 20210157753
- Publication date May 27, 2021
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
USING A SECOND CONTENT-ADDRESSABLE MEMORY TO MANAGE MEMORY BURST AC...
- Publication number 20200201776
- Publication date Jun 25, 2020
- Micron Technology, Inc.
- Laurent Isenegger
- G06 - COMPUTING CALCULATING COUNTING

Laurent Isenegger

Person

Patents Grantslast 30 patents

Write request buffer capable of responding to read requests

Request control for memory sub-systems

Command scheduling component for memory

Interleaved cache prefetching

Write request thresholding

Using a second content-addressable memory to manage memory burst ac...

Memory-flow control register

Outstanding transaction monitoring for memory sub-systems

Dynamic queue depth adjustment

Direct memory access (DMA) commands for noncontiguous source and de...

Interleaved cache prefetching

Request control for memory sub-systems

Quality of service levels for a direct memory access engine in a me...

Using a second content-addressable memory to manage memory burst ac...

Managing processing of memory commands in a memory subsystem with a...

Managing memory commands in a memory subsystem by adjusting a maxim...

Direct memory access (DMA) commands for noncontiguous source and de...

Quality of service levels for a direct memory access engine in a me...

Patents Applicationslast 30 patents

COMMAND SCHEDULING COMPONENT FOR MEMORY

REQUEST CONTROL FOR MEMORY SUB-SYSTEMS

INTERLEAVED CACHE PREFETCHING

Write Request Buffer

Memory-Flow Control Register

OUTSTANDING TRANSACTION MONITORING FOR MEMORY SUB-SYSTEMS

INTERLEAVED CACHE PREFETCHING

REQUEST CONTROL FOR MEMORY SUB-SYSTEMS

WRITE REQUEST THRESHOLDING

COMMAND RETRIEVAL AND ISSUANCE POLICY

COMMAND SCHEDULING COMPONENT FOR MEMORY

DYNAMIC QUEUE DEPTH ADJUSTMENT

USING A SECOND CONTENT-ADDRESSABLE MEMORY TO MANAGE MEMORY BURST AC...

MANAGING PROCESSING OF MEMORY COMMANDS IN A MEMORY SUBSYSTEM WITH A...

DIRECT MEMORY ACCESS (DMA) COMMANDS FOR NONCONTIGUOUS SOURCE AND DE...

QUALITY OF SERVICE LEVELS FOR A DIRECT MEMORY ACCESS ENGINE IN A ME...

DIRECT MEMORY ACCESS (DMA) COMMANDS FOR NONCONTIGUOUS SOURCE AND DE...

USING A SECOND CONTENT-ADDRESSABLE MEMORY TO MANAGE MEMORY BURST AC...