Laurent Souef

Person

Mouans Sartoux, FR

People

Patents Grantslast 30 patents

Information Patent Grant
Scan testing methods
- Patent number 7,870,452
- Issue date Jan 11, 2011
- NXP B.V.
- Laurent Souef
- G01 - MEASURING TESTING
Information Patent Grant
Cell with fixed output voltage for integrated circuit
- Patent number 7,688,103
- Issue date Mar 30, 2010
- NXP B.V.
- Patrick Da Silva
- G01 - MEASURING TESTING
Information Patent Grant
Cell with fixed output voltage for integrated circuit
- Patent number 7,459,928
- Issue date Dec 2, 2008
- NXP B.V.
- Patrick Da Silva
- G01 - MEASURING TESTING
Information Patent Grant
Method of discriminating between different types of scan failures,...
- Patent number 6,970,815
- Issue date Nov 29, 2005
- Koninklijke Philips Electronics N.V.
- Jerome Bombal
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Computer implemented circuit synthesis system
- Patent number 6,671,870
- Issue date Dec 30, 2003
- Koninklijke Philips Electronics N.V.
- Laurent Souef
- G01 - MEASURING TESTING
Information Patent Grant
Design for test area optimization algorithm
- Patent number 6,311,318
- Issue date Oct 30, 2001
- VLSI Technology, Inc.
- Laurent Souef
- G01 - MEASURING TESTING
Information Patent Grant
Pseudo-scan testing using hardware-accessible IC structures
- Patent number 6,141,782
- Issue date Oct 31, 2000
- VLSI Technology, Inc.
- Jerome Bombal
- G01 - MEASURING TESTING
Information Patent Grant
Low power scannable counter
- Patent number 5,960,052
- Issue date Sep 28, 1999
- VLSI Technology, Inc.
- Jerome Bombal
- G01 - MEASURING TESTING

Patents Applicationslast 30 patents

Information Patent Application
TESTABLE INTEGRATED CIRCUIT AND TEST METHOD
- Publication number 20100182033
- Publication date Jul 22, 2010
- NXP B.V.
- Laurent Souef
- G01 - MEASURING TESTING
Information Patent Application
Cell with Fixed Output Voltage for Integrated Circuit
- Publication number 20090051385
- Publication date Feb 26, 2009
- NXP, B.V.
- Patrick Da Silva
- G01 - MEASURING TESTING
Information Patent Application
Scan Testing Methods
- Publication number 20080250288
- Publication date Oct 9, 2008
- NXP B.V.
- Laurent Souef
- G01 - MEASURING TESTING
Information Patent Application
Cell with fixed output voltage for integrated circuit
- Publication number 20050180196
- Publication date Aug 18, 2005
- Koninklijke Philips Electronics N.V.
- Patrick Da Silva
- G01 - MEASURING TESTING
Information Patent Application
Method of testing an integrated circuit by simulation
- Publication number 20030128022
- Publication date Jul 10, 2003
- Laurent Souef
- G01 - MEASURING TESTING
Information Patent Application
Clock-skew resistant chain of sequential cells
- Publication number 20020145458
- Publication date Oct 10, 2002
- Frederic Natali
- G01 - MEASURING TESTING
Information Patent Application
Computer implemented circuit synthesis system
- Publication number 20020032898
- Publication date Mar 14, 2002
- Laurent Souef
- G01 - MEASURING TESTING

Laurent Souef

Person

Patents Grantslast 30 patents

Scan testing methods

Cell with fixed output voltage for integrated circuit

Cell with fixed output voltage for integrated circuit

Method of discriminating between different types of scan failures,...

Computer implemented circuit synthesis system

Design for test area optimization algorithm

Pseudo-scan testing using hardware-accessible IC structures

Low power scannable counter

Patents Applicationslast 30 patents

TESTABLE INTEGRATED CIRCUIT AND TEST METHOD

Cell with Fixed Output Voltage for Integrated Circuit

Scan Testing Methods

Cell with fixed output voltage for integrated circuit

Method of testing an integrated circuit by simulation

Clock-skew resistant chain of sequential cells

Computer implemented circuit synthesis system