Laurin Ashby

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Mesa, AZ, US

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Patents Grantslast 30 patents

Information Patent Grant
Interface control logic for embedding a microprocessor in a gate array
- Patent number 5,347,181
- Issue date Sep 13, 1994
- Motorola, Inc.
- Laurin R. Ashby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method for powering down a microprocessor embedded within a gate array
- Patent number 5,304,860
- Issue date Apr 19, 1994
- Motorola, Inc.
- Laurin R. Ashby
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Phase detector with deadzone window
- Patent number 5,121,010
- Issue date Jun 9, 1992
- Motorola, Inc.
- Gary W. Hoshizaki
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital delay line with inverter tap resolution
- Patent number 5,095,233
- Issue date Mar 10, 1992
- Motorola, Inc.
- Laurin Ashby
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Digital phase lock loop for a gate array
- Patent number 5,079,519
- Issue date Jan 7, 1992
- Notorola, Inc.
- Laurin Ashby
- G06 - COMPUTING CALCULATING COUNTING