Lavi Koch

Person

Jerusalem, IL

People

Patents Grantslast 30 patents

Information Patent Grant
Synthesized clock synchronization between network devices
- Patent number 11,637,557
- Issue date Apr 25, 2023
- Mellanox Technologies, Ltd.
- Ran Ravid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Enhancing port link-up time
- Patent number 11,349,780
- Issue date May 31, 2022
- Mellanox Technologies, Ltd.
- Sagi Rotem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synthesized clock synchronization between network devices
- Patent number 11,283,454
- Issue date Mar 22, 2022
- Mellanox Technologies, Ltd.
- Ran Ravid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Network devices
- Patent number 10,951,545
- Issue date Mar 16, 2021
- MELLANOX TECHNOLOGIES TLV LTD.
- Barak Gafni
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Raising maximal silicon die temperature using reliability model
- Patent number 10,915,154
- Issue date Feb 9, 2021
- MELLANOX TECHNOLOGIES TLV LTD.
- George Elias
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Synthesized clock synchronization between networks devices
- Patent number 10,778,406
- Issue date Sep 15, 2020
- Mellanox Technologies, Ltd.
- Chen Gaist
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Grant
Accessing PCIe configuration data through network
- Patent number 10,503,682
- Issue date Dec 10, 2019
- Mellanox Technologies, Ltd.
- Yoni Galezer
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Power-efficient activation of multi-lane ports in a network element
- Patent number 10,412,673
- Issue date Sep 10, 2019
- Mellanox Technologies TLV Ltd.
- Gil Levy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Control of peripheral device data exchange based on CPU power state
- Patent number 10,324,513
- Issue date Jun 18, 2019
- Mellanox Technologies, Ltd.
- Idan Burstein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit and method for reducing violations of a timing c...
- Patent number 8,706,928
- Issue date Apr 22, 2014
- FREESCALE SEMICONDUCTOR, INC.
- Roman Mostinski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Method of low power PLL for low jitter demanding applications
- Patent number 7,786,809
- Issue date Aug 31, 2010
- Freescale
- Michael Priel
- H03 - BASIC ELECTRONIC CIRCUITRY
Information Patent Grant
Method for generating a output clock signal having a output cycle a...
- Patent number 7,688,127
- Issue date Mar 30, 2010
- FREESCALE SEMICONDUCTOR, INC.
- Michael Priel
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
Link Training for Multi-Segment Communication Networks
- Publication number 20240056380
- Publication date Feb 15, 2024
- MELLANOX TECHNOLOGIES, LTD.
- Zvi Rechtman
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Link efficient power state management for multi-segment switched fa...
- Publication number 20240039689
- Publication date Feb 1, 2024
- MELLANOX TECHNOLOGIES, LTD.
- Roman Meltser
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Synthesized clock synchronization between network devices
- Publication number 20220173741
- Publication date Jun 2, 2022
- MELLANOX TECHNOLOGIES, LTD.
- Ran Ravid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Enhancing Port Link-up Time
- Publication number 20220070117
- Publication date Mar 3, 2022
- MELLANOX TECHNOLOGIES, LTD.
- Sagi Rotem
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Synthesized Clock Synchronization Between Network Devices
- Publication number 20220021393
- Publication date Jan 20, 2022
- MELLANOX TECHNOLOGIES, LTD.
- Ran Ravid
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Raising Maximal Silicon Die Temperature Using Reliability Model
- Publication number 20210041927
- Publication date Feb 11, 2021
- Mellanox Technologies TLV Ltd.
- George Elias
- G05 - CONTROLLING REGULATING
Information Patent Application
Network devices
- Publication number 20200328987
- Publication date Oct 15, 2020
- Mellanox Technologies TLV Ltd.
- Barak Gafni
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Synthesized Clock Synchronization Between Network Devices
- Publication number 20200169379
- Publication date May 28, 2020
- MELLANOX TECHNOLOGIES, LTD.
- Chen Gaist
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
Power-Efficient Activation of Multi-Lane Ports in a Network Element
- Publication number 20180343613
- Publication date Nov 29, 2018
- Mellanox Technologies TLV Ltd.
- Gil Levy
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Fabric Wise Width Reduction
- Publication number 20180199292
- Publication date Jul 12, 2018
- Mellanox Technologies TLV Ltd.
- Liron Mula
- H04 - ELECTRIC COMMUNICATION TECHNIQUE
Information Patent Application
CONTROL OF PERIPHERAL DEVICE DATA EXCHANGE BASED ON CPU POWER STATE
- Publication number 20160062442
- Publication date Mar 3, 2016
- MELLANOX TECHNOLOGIES LTD.
- Idan Burstein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTEGRATED CIRCUIT AND METHOD FOR REDUCING VIOLATIONS OF A TIMING C...
- Publication number 20120226833
- Publication date Sep 6, 2012
- FREESCALE SEMICONDUCTOR, INC.
- Roman Mostinski
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHOD FOR GENERATING A OUTPUT CLOCK SIGNAL HAVING A OUTPUT CYCLE A...
- Publication number 20100019821
- Publication date Jan 28, 2010
- Michael Priel
- G06 - COMPUTING CALCULATING COUNTING

Person

Patents Grantslast 30 patents

Synthesized clock synchronization between network devices

Enhancing port link-up time

Synthesized clock synchronization between network devices

Network devices

Raising maximal silicon die temperature using reliability model

Synthesized clock synchronization between networks devices

Accessing PCIe configuration data through network

Power-efficient activation of multi-lane ports in a network element

Control of peripheral device data exchange based on CPU power state

Integrated circuit and method for reducing violations of a timing c...

Method of low power PLL for low jitter demanding applications

Method for generating a output clock signal having a output cycle a...

Patents Applicationslast 30 patents

Link Training for Multi-Segment Communication Networks

Link efficient power state management for multi-segment switched fa...

Synthesized clock synchronization between network devices

Enhancing Port Link-up Time

Synthesized Clock Synchronization Between Network Devices

Raising Maximal Silicon Die Temperature Using Reliability Model

Network devices

Synthesized Clock Synchronization Between Network Devices

Power-Efficient Activation of Multi-Lane Ports in a Network Element

Fabric Wise Width Reduction

CONTROL OF PERIPHERAL DEVICE DATA EXCHANGE BASED ON CPU POWER STATE

INTEGRATED CIRCUIT AND METHOD FOR REDUCING VIOLATIONS OF A TIMING C...

METHOD FOR GENERATING A OUTPUT CLOCK SIGNAL HAVING A OUTPUT CYCLE A...