Leathen Shi

Person

Yorktown Heights, NY, US

People

Patents Grantslast 30 patents

Information Patent Grant
Wafer level integration including design/co-design, structure proce...
- Patent number 10,811,305
- Issue date Oct 20, 2020
- International Business Machines Corporation
- Li-Wen Hung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including built-in crack-arresting film structure
- Patent number 10,615,139
- Issue date Apr 7, 2020
- International Business Machines Corporation
- Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including built-in crack-arresting film structure
- Patent number 10,211,178
- Issue date Feb 19, 2019
- International Business Machines Corporation
- Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including built-in crack-arresting film structure
- Patent number 10,020,279
- Issue date Jul 10, 2018
- International Business Machines Corporation
- Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Epitaxial lift-off process with guided etching
- Patent number 9,865,469
- Issue date Jan 9, 2018
- International Business Machines Corporation
- Cheng-Wei Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Epitaxial lift-off process with guided etching
- Patent number 9,653,308
- Issue date May 16, 2017
- International Business Machines Corporation
- Cheng-Wei Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Semiconductor device including built-in crack-arresting film structure
- Patent number 9,536,853
- Issue date Jan 3, 2017
- International Business Machines Corporation
- Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flattened substrate surface for substrate bonding
- Patent number 9,355,936
- Issue date May 31, 2016
- GLOBALFOUNDRIES Inc.
- Edward C. Cooney
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Accurate control of distance between suspended semiconductor nanowi...
- Patent number 8,927,405
- Issue date Jan 6, 2015
- International Business Machines Corporation
- Guy Cohen
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Accurate control of distance between suspended semiconductor nanowi...
- Patent number 8,927,968
- Issue date Jan 6, 2015
- International Business Machines Corporation
- Guy Cohen
- B82 - NANO-TECHNOLOGY
Information Patent Grant
Low cost fabrication of double box back gate silicon-on-insulator w...
- Patent number 8,877,606
- Issue date Nov 4, 2014
- International Business Machines Corporation
- Robert H. Dennard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Flattened substrate surface for substrate bonding
- Patent number 8,778,737
- Issue date Jul 15, 2014
- International Business Machines Corporation
- Edward C. Cooney
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High-k dielectric and silicon nitride box region
- Patent number 8,637,381
- Issue date Jan 28, 2014
- International Business Machines Corporation
- Effendi Leobandung
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of forming isolation structures for SOI devices with ultrath...
- Patent number 8,586,426
- Issue date Nov 19, 2013
- International Business Machines Corporation
- Robert H. Dennard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Isolation structures for SOI devices with ultrathin SOI and ultrath...
- Patent number 8,492,838
- Issue date Jul 23, 2013
- International Business Machines Corporation
- Robert H. Dennard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Adaptive chuck for planar bonding between substrates
- Patent number 8,408,262
- Issue date Apr 2, 2013
- International Business Machines Corporation
- Dechao Guo
- B32 - LAYERED PRODUCTS
Information Patent Grant
Back-gated fully depleted SOI transistor
- Patent number 8,030,145
- Issue date Oct 4, 2011
- International Business Machines Corporation
- Leland Chang
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Grant
Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
- Patent number 8,017,499
- Issue date Sep 13, 2011
- International Business Machines Corporation
- Kevin K. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Preparation of high quality strained-semiconductor directly-on-insu...
- Patent number 7,897,480
- Issue date Mar 1, 2011
- International Business Machines Corporation
- Jack O. Chu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Low cost fabrication of double box back gate silicon-on-insulator w...
- Patent number 7,767,546
- Issue date Aug 3, 2010
- International Business Machines Corporation
- Robert H. Dennard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low temperature fusion bonding with high surface energy using a wet...
- Patent number 7,713,837
- Issue date May 11, 2010
- International Business Machines Corporation
- Kevin K. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of creating defect free high Ge content (>25%) SiGe-on-insul...
- Patent number 7,704,815
- Issue date Apr 27, 2010
- International Business Machines Corporation
- Jack O. Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained silicon CMOS on hybrid crystal orientations
- Patent number 7,691,688
- Issue date Apr 6, 2010
- International Business Machines Corporation
- Kevin K. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low temperature fusion bonding with high surface energy using a wet...
- Patent number 7,566,631
- Issue date Jul 28, 2009
- International Business Machines Corporation
- Kevin K. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Low-cost strained SOI substrate for high-performance CMOS technology
- Patent number 7,528,056
- Issue date May 5, 2009
- International Business Machines Corporation
- Meikei Ieong
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Multiple layer and crystal plane orientation semiconductor substrate
- Patent number 7,521,735
- Issue date Apr 21, 2009
- International Business Machines Corporation
- Toshiharu Furukawa
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
- Patent number 7,507,989
- Issue date Mar 24, 2009
- International Business Machines Corporation
- Kevin K. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method for preparing 2-dimensional semiconductor devices for integr...
- Patent number 7,488,630
- Issue date Feb 10, 2009
- International Business Machines Corporation
- David J. Frank
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)
- Patent number 7,485,518
- Issue date Feb 3, 2009
- International Business Machines Corporation
- Kevin K. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method of creating defect free high Ge content (> 25%) SiGe-on-insu...
- Patent number 7,445,977
- Issue date Nov 4, 2008
- International Business Machines Corporation
- Jack O. Chu
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING BUILT-IN CRACK-ARRESTING FILM STRUCTURE
- Publication number 20180226374
- Publication date Aug 9, 2018
- International Business Machines Corporation
- Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCE...
- Publication number 20180082888
- Publication date Mar 22, 2018
- International Business Machines Corporation
- Li-Wen HUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING BUILT-IN CRACK-ARRESTING FILM STRUCTURE
- Publication number 20170221850
- Publication date Aug 3, 2017
- International Business Machines Corporation
- Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EPITAXIAL LIFT-OFF PROCESS WITH GUIDED ETCHING
- Publication number 20170154783
- Publication date Jun 1, 2017
- International Business Machines Corporation
- Cheng-Wei Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
EPITAXIAL LIFT-OFF PROCESS WITH GUIDED ETCHING
- Publication number 20170062232
- Publication date Mar 2, 2017
- International Business Machines Corporation
- Cheng-Wei Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING BUILT-IN CRACK-ARRESTING FILM STRUCTURE
- Publication number 20160322324
- Publication date Nov 3, 2016
- International Business Machines Corporation
- Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SEMICONDUCTOR DEVICE INCLUDING BUILT-IN CRACK-ARRESTING FILM STRUCTURE
- Publication number 20160141263
- Publication date May 19, 2016
- International Business Machines Corporation
- Wei Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING
- Publication number 20140209908
- Publication date Jul 31, 2014
- International Business Machines Corporation
- Edward C. Cooney
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ACCURATE CONTROL OF DISTANCE BETWEEN SUSPENDED SEMICONDUCTOR NANOWI...
- Publication number 20140166983
- Publication date Jun 19, 2014
- International Business Machines Corporation
- Guy Cohen
- B82 - NANO-TECHNOLOGY
Information Patent Application
ACCURATE CONTROL OF DISTANCE BETWEEN SUSPENDED SEMICONDUCTOR NANOWI...
- Publication number 20140166982
- Publication date Jun 19, 2014
- International Business Machines Corporation
- Guy Cohen
- B82 - NANO-TECHNOLOGY
Information Patent Application
SOI STRUCTURES INCLUDING A BURIED BORON NITRIDE DIELECTRIC
- Publication number 20130196483
- Publication date Aug 1, 2013
- International Business Machines Corporation
- Robert H. Dennard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SOI STRUCTURES INCLUDING A BURIED BORON NITRIDE DIELECTRIC
- Publication number 20130193445
- Publication date Aug 1, 2013
- International Business Machines Corporation
- Robert H. Dennard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING
- Publication number 20130105981
- Publication date May 2, 2013
- International Business Machines Corporation
- Edward C. Cooney
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH-K DIELECTRIC AND SILICON NITRIDE BOX REGION
- Publication number 20130093039
- Publication date Apr 18, 2013
- International Business Machines Corporation
- EFFENDI LEOBANDUNG
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADAPTIVE CHUCK FOR PLANAR BONDING BETWEEN SUBSTRATES
- Publication number 20120312452
- Publication date Dec 13, 2012
- International Business Machines Corporation
- Dechao Guo
- B32 - LAYERED PRODUCTS
Information Patent Application
ISOLATION STRUCTURES FOR SOI DEVICES WITH ULTRATHIN SOI AND ULTRATH...
- Publication number 20120302039
- Publication date Nov 29, 2012
- International Business Machines Corporation
- Robert H. Dennard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR W...
- Publication number 20120112309
- Publication date May 10, 2012
- International Business Machines Corporation
- Robert H. Dennard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
BACK-GATED FULLY DEPLETED SOI TRANSISTOR
- Publication number 20110171792
- Publication date Jul 14, 2011
- International Business Machines Corporation
- Leland Chang
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
ISOLATION STRUCTURES FOR SOI DEVICES WITH ULTRATHIN SOI AND ULTRATH...
- Publication number 20110115021
- Publication date May 19, 2011
- International Business Machines Corporation
- Robert H. Dennard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADAPTIVE CHUCK FOR PLANAR BONDING BETWEEN SUBSTRATES
- Publication number 20110083786
- Publication date Apr 14, 2011
- International Business Machines Corporation
- Dechao Guo
- B32 - LAYERED PRODUCTS
Information Patent Application
LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR W...
- Publication number 20100187607
- Publication date Jul 29, 2010
- International Business Machines Corporation
- Robert H. Dennard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR W...
- Publication number 20100176453
- Publication date Jul 15, 2010
- International Business Machines Corporation
- Robert H. Dennard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR W...
- Publication number 20100176482
- Publication date Jul 15, 2010
- International Business Machine Corporation
- Robert H. Dennard
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR W...
- Publication number 20100176495
- Publication date Jul 15, 2010
- International Business Machines Corporation
- Jack O. Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD OF CREATING DEFECT FREE HIGH Ge CONTENT (> 25%) SiGe-ON-INSU...
- Publication number 20090004831
- Publication date Jan 1, 2009
- International Business Machines Corporation
- Jack O. Chu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PREPARATION OF HIGH QUALITY STRAINED-SEMICONDUCTOR DIRECTLY-ON-INSU...
- Publication number 20080261055
- Publication date Oct 23, 2008
- International Business Machines Corporation
- Jack O. Chu
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
STRAINED SILICON CMOS ON HYBRID CRYSTAL ORIENTATIONS
- Publication number 20080254594
- Publication date Oct 16, 2008
- International Business Machines Corporation
- Kevin K. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
LOW TEMPERATURE FUSION BONDING WITH HIGH SURFACE ENERGY USING A WET...
- Publication number 20080227270
- Publication date Sep 18, 2008
- International Business Machines Corporation
- Kevin K. Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD FOR PREPARING 2-DIMENSIONAL SEMICONDUCTOR DEVICES FOR INTEGR...
- Publication number 20080217782
- Publication date Sep 11, 2008
- International Business Machines Corporation
- David J. Frank
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
STRAINED Si MOSFET ON TENSILE-STRAINED SiGe-ON-INSULATOR (SGOI)
- Publication number 20080220588
- Publication date Sep 11, 2008
- International Business Machines Corporation
- Kevin K. Chan
- H01 - BASIC ELECTRIC ELEMENTS

Leathen Shi

Person

Patents Grantslast 30 patents

Wafer level integration including design/co-design, structure proce...

Semiconductor device including built-in crack-arresting film structure

Semiconductor device including built-in crack-arresting film structure

Semiconductor device including built-in crack-arresting film structure

Epitaxial lift-off process with guided etching

Epitaxial lift-off process with guided etching

Semiconductor device including built-in crack-arresting film structure

Flattened substrate surface for substrate bonding

Accurate control of distance between suspended semiconductor nanowi...

Accurate control of distance between suspended semiconductor nanowi...

Low cost fabrication of double box back gate silicon-on-insulator w...

Flattened substrate surface for substrate bonding

High-k dielectric and silicon nitride box region

Method of forming isolation structures for SOI devices with ultrath...

Isolation structures for SOI devices with ultrathin SOI and ultrath...

Adaptive chuck for planar bonding between substrates

Back-gated fully depleted SOI transistor

Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)

Preparation of high quality strained-semiconductor directly-on-insu...

Low cost fabrication of double box back gate silicon-on-insulator w...

Low temperature fusion bonding with high surface energy using a wet...

Method of creating defect free high Ge content (>25%) SiGe-on-insul...

Strained silicon CMOS on hybrid crystal orientations

Low temperature fusion bonding with high surface energy using a wet...

Low-cost strained SOI substrate for high-performance CMOS technology

Multiple layer and crystal plane orientation semiconductor substrate

Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)

Method for preparing 2-dimensional semiconductor devices for integr...

Strained Si MOSFET on tensile-strained SiGe-on-insulator (SGOI)

Method of creating defect free high Ge content (> 25%) SiGe-on-insu...

Patents Applicationslast 30 patents

SEMICONDUCTOR DEVICE INCLUDING BUILT-IN CRACK-ARRESTING FILM STRUCTURE

WAFER LEVEL INTEGRATION INCLUDING DESIGN/CO-DESIGN, STRUCTURE PROCE...

SEMICONDUCTOR DEVICE INCLUDING BUILT-IN CRACK-ARRESTING FILM STRUCTURE

EPITAXIAL LIFT-OFF PROCESS WITH GUIDED ETCHING

EPITAXIAL LIFT-OFF PROCESS WITH GUIDED ETCHING

SEMICONDUCTOR DEVICE INCLUDING BUILT-IN CRACK-ARRESTING FILM STRUCTURE

SEMICONDUCTOR DEVICE INCLUDING BUILT-IN CRACK-ARRESTING FILM STRUCTURE

FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING

ACCURATE CONTROL OF DISTANCE BETWEEN SUSPENDED SEMICONDUCTOR NANOWI...

ACCURATE CONTROL OF DISTANCE BETWEEN SUSPENDED SEMICONDUCTOR NANOWI...

SOI STRUCTURES INCLUDING A BURIED BORON NITRIDE DIELECTRIC

SOI STRUCTURES INCLUDING A BURIED BORON NITRIDE DIELECTRIC

FLATTENED SUBSTRATE SURFACE FOR SUBSTRATE BONDING

HIGH-K DIELECTRIC AND SILICON NITRIDE BOX REGION

ADAPTIVE CHUCK FOR PLANAR BONDING BETWEEN SUBSTRATES

ISOLATION STRUCTURES FOR SOI DEVICES WITH ULTRATHIN SOI AND ULTRATH...

LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR W...

BACK-GATED FULLY DEPLETED SOI TRANSISTOR

ISOLATION STRUCTURES FOR SOI DEVICES WITH ULTRATHIN SOI AND ULTRATH...

ADAPTIVE CHUCK FOR PLANAR BONDING BETWEEN SUBSTRATES

LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR W...

LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR W...

LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR W...

LOW COST FABRICATION OF DOUBLE BOX BACK GATE SILICON-ON-INSULATOR W...

METHOD OF CREATING DEFECT FREE HIGH Ge CONTENT (> 25%) SiGe-ON-INSU...

PREPARATION OF HIGH QUALITY STRAINED-SEMICONDUCTOR DIRECTLY-ON-INSU...

STRAINED SILICON CMOS ON HYBRID CRYSTAL ORIENTATIONS

LOW TEMPERATURE FUSION BONDING WITH HIGH SURFACE ENERGY USING A WET...

METHOD FOR PREPARING 2-DIMENSIONAL SEMICONDUCTOR DEVICES FOR INTEGR...

STRAINED Si MOSFET ON TENSILE-STRAINED SiGe-ON-INSULATOR (SGOI)