Lee D. Whetsel

Person

Parker, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Test compression in a JTAG daisy-chain environment
- Patent number 11,965,930
- Issue date Apr 23, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Shadow access port method and apparatus
- Patent number 11,906,582
- Issue date Feb 20, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scan testing using scan frames with embedded commands
- Patent number 11,879,941
- Issue date Jan 23, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Reduced signaling interface method and apparatus
- Patent number 11,867,756
- Issue date Jan 9, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interposer instrumentation method and apparatus
- Patent number 11,860,224
- Issue date Jan 2, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Two pin serial bus communication interface and process
- Patent number 11,854,654
- Issue date Dec 26, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device testing architecture, method, and system
- Patent number 11,846,673
- Issue date Dec 19, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
TSV testing method and apparatus
- Patent number 11,835,573
- Issue date Dec 5, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interposer circuit
- Patent number 11,835,581
- Issue date Dec 5, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selectable JTAG or trace access with data store and output
- Patent number 11,835,578
- Issue date Dec 5, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
AT-speed test access port operations
- Patent number 11,808,810
- Issue date Nov 7, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,782,091
- Issue date Oct 10, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with reduced signaling interface
- Patent number 11,768,238
- Issue date Sep 26, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D TAP and scan port architectures
- Patent number 11,762,014
- Issue date Sep 19, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Addressable test access port apparatus
- Patent number 11,747,397
- Issue date Sep 5, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scan testing using scan frames with embedded commands
- Patent number 11,740,286
- Issue date Aug 29, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit die test architecture
- Patent number 11,726,135
- Issue date Aug 15, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Direct scan access JTAG
- Patent number 11,693,055
- Issue date Jul 4, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Falling clock edge JTAG bus routers
- Patent number 11,680,985
- Issue date Jun 20, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Test access port with address and command capability
- Patent number 11,680,981
- Issue date Jun 20, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
3D stacked die test architecture
- Patent number 11,675,007
- Issue date Jun 13, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Apparatus for device access port selection
- Patent number 11,656,278
- Issue date May 23, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Testing interposer method and apparatus
- Patent number 11,644,482
- Issue date May 9, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- B05 - SPRAYING OR ATOMISING IN GENERAL APPLYING LIQUIDS OR OTHER FLUENT MATER...
Information Patent Grant
TSV testing using test circuits and grounding means
- Patent number 11,644,503
- Issue date May 9, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Test compression in a JTAG daisy-chain environment
- Patent number 11,639,963
- Issue date May 2, 2023
- Texas Instmments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scan frame based test access mechanisms
- Patent number 11,635,464
- Issue date Apr 25, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Interface to full and reduced pin JTAG devices
- Patent number 11,630,151
- Issue date Apr 18, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Device testing architecture of an integrated circuit
- Patent number 11,609,269
- Issue date Mar 21, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Commanded JTAG test access port operations
- Patent number 11,604,222
- Issue date Mar 14, 2023
- Texas Instmments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
IEEE 1149.1 interposer apparatus
- Patent number 11,585,851
- Issue date Feb 21, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
INTERPOSER INSTRUMENTATION METHOD AND APPARATUS
- Publication number 20240133947
- Publication date Apr 25, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TSV TESTING
- Publication number 20240094280
- Publication date Mar 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERPOSER CIRCUIT
- Publication number 20240094289
- Publication date Mar 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AT-SPEED TEST ACCESS PORT OPERATIONS
- Publication number 20240061038
- Publication date Feb 22, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
- Publication number 20240019489
- Publication date Jan 18, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS
- Publication number 20240012050
- Publication date Jan 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20230417831
- Publication date Dec 28, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
ADDRESSABLE TEST ACCESS PORT
- Publication number 20230400513
- Publication date Dec 14, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS
- Publication number 20230384376
- Publication date Nov 30, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
- Publication number 20230366920
- Publication date Nov 16, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
FALLING CLOCK EDGE JTAG BUS ROUTERS
- Publication number 20230333163
- Publication date Oct 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY
- Publication number 20230333159
- Publication date Oct 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20230324812
- Publication date Oct 12, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
DEVICE ACCESS PORT SELECTION
- Publication number 20230296670
- Publication date Sep 21, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TESTING INTERPOSER METHOD AND APPARATUS
- Publication number 20230273238
- Publication date Aug 31, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- B05 - SPRAYING OR ATOMISING IN GENERAL APPLYING LIQUIDS OR OTHER FLUENT MATER...
Information Patent Application
Array of Through-Silicon Via Contact Points on a Semiconductor Die
- Publication number 20230273258
- Publication date Aug 31, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT
- Publication number 20230266389
- Publication date Aug 24, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN FRAME BASED TEST ACCESS MECHANISMS
- Publication number 20230258715
- Publication date Aug 17, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES
- Publication number 20230251309
- Publication date Aug 10, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM
- Publication number 20230228814
- Publication date Jul 20, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
COMMANDED JTAG TEST ACCESS PORT OPERATIONS
- Publication number 20230221368
- Publication date Jul 13, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
INTERPOSER CIRCUIT
- Publication number 20230204663
- Publication date Jun 29, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SHADOW ACCESS PORT METHOD AND APPARATUS
- Publication number 20230194603
- Publication date Jun 22, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
AT-SPEED TEST ACCESS PORT OPERATIONS
- Publication number 20230194604
- Publication date Jun 22, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGIS...
- Publication number 20230176123
- Publication date Jun 8, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE
- Publication number 20230160959
- Publication date May 25, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20230160958
- Publication date May 25, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
REDUCED SIGNALING INTERFACE METHOD & APPARATUS
- Publication number 20230058458
- Publication date Feb 23, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
APPARATUS FOR DEVICE ACCESS PORT SELECTION
- Publication number 20220413041
- Publication date Dec 29, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20220381821
- Publication date Dec 1, 2022
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING

Lee D. Whetsel

Person

Patents Grantslast 30 patents

Test compression in a JTAG daisy-chain environment

Shadow access port method and apparatus

Scan testing using scan frames with embedded commands

Reduced signaling interface method and apparatus

Interposer instrumentation method and apparatus

Two pin serial bus communication interface and process

Device testing architecture, method, and system

TSV testing method and apparatus

Interposer circuit

Selectable JTAG or trace access with data store and output

AT-speed test access port operations

Wafer scale testing using a 2 signal JTAG interface

Integrated circuit with reduced signaling interface

3D TAP and scan port architectures

Addressable test access port apparatus

Scan testing using scan frames with embedded commands

Integrated circuit die test architecture

Direct scan access JTAG

Falling clock edge JTAG bus routers

Test access port with address and command capability

3D stacked die test architecture

Apparatus for device access port selection

Testing interposer method and apparatus

TSV testing using test circuits and grounding means

Test compression in a JTAG daisy-chain environment

Scan frame based test access mechanisms

Interface to full and reduced pin JTAG devices

Device testing architecture of an integrated circuit

Commanded JTAG test access port operations

IEEE 1149.1 interposer apparatus

Patents Applicationslast 30 patents

INTERPOSER INSTRUMENTATION METHOD AND APPARATUS

TSV TESTING

INTERPOSER CIRCUIT

AT-SPEED TEST ACCESS PORT OPERATIONS

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

3D TAP & SCAN PORT ARCHITECTURES

ADDRESSABLE TEST ACCESS PORT

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

FALLING CLOCK EDGE JTAG BUS ROUTERS

TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY

3D STACKED DIE TEST ARCHITECTURE

DEVICE ACCESS PORT SELECTION

TESTING INTERPOSER METHOD AND APPARATUS

Array of Through-Silicon Via Contact Points on a Semiconductor Die

TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT

SCAN FRAME BASED TEST ACCESS MECHANISMS

INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES

DEVICE TESTING ARCHITECTURE, METHOD, AND SYSTEM

COMMANDED JTAG TEST ACCESS PORT OPERATIONS

INTERPOSER CIRCUIT

SHADOW ACCESS PORT METHOD AND APPARATUS

AT-SPEED TEST ACCESS PORT OPERATIONS

PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGIS...

WAFER SCALE TESTING USING A 2 SIGNAL JTAG INTERFACE

3D TAP & SCAN PORT ARCHITECTURES

REDUCED SIGNALING INTERFACE METHOD & APPARATUS

APPARATUS FOR DEVICE ACCESS PORT SELECTION

3D STACKED DIE TEST ARCHITECTURE