Lee D. Whetsel

Person

Parker, TX, US

People

Patents Grantslast 30 patents

Information Patent Grant
Interposer circuit
- Patent number 12,352,814
- Issue date Jul 8, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrated circuit die test architecture
- Patent number 12,313,667
- Issue date May 27, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Device access port selection
- Patent number 12,210,060
- Issue date Jan 28, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Test access port with address and command capability
- Patent number 12,188,980
- Issue date Jan 7, 2025
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
At-speed test access port operations
- Patent number 12,181,521
- Issue date Dec 31, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D tap and scan port architectures
- Patent number 12,164,001
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
TSV testing
- Patent number 12,163,998
- Issue date Dec 10, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Scan testable through silicon VIAs
- Patent number 12,154,835
- Issue date Nov 26, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Commanded JTAG test access port operations
- Patent number 12,153,090
- Issue date Nov 26, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Selectable JTAG or trace access with data store and output
- Patent number 12,146,909
- Issue date Nov 19, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interface to full and reduced pin JTAG devices
- Patent number 12,130,328
- Issue date Oct 29, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scan frame based test access mechanisms
- Patent number 12,117,490
- Issue date Oct 15, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Selectable JTAG or trace access with data store and output
- Patent number 12,092,687
- Issue date Sep 17, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Addressable test access port
- Patent number 12,050,247
- Issue date Jul 30, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Integrated circuit die test architecture
- Patent number 12,025,649
- Issue date Jul 2, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Programmable test compression architecture input/output shift regis...
- Patent number 12,013,434
- Issue date Jun 18, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
3D stacked die test architecture
- Patent number 12,007,441
- Issue date Jun 11, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Test compression in a JTAG daisy-chain environment
- Patent number 11,965,930
- Issue date Apr 23, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Shadow access port method and apparatus
- Patent number 11,906,582
- Issue date Feb 20, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Scan testing using scan frames with embedded commands
- Patent number 11,879,941
- Issue date Jan 23, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Reduced signaling interface method and apparatus
- Patent number 11,867,756
- Issue date Jan 9, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Interposer instrumentation method and apparatus
- Patent number 11,860,224
- Issue date Jan 2, 2024
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
Two pin serial bus communication interface and process
- Patent number 11,854,654
- Issue date Dec 26, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Device testing architecture, method, and system
- Patent number 11,846,673
- Issue date Dec 19, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Grant
TSV testing method and apparatus
- Patent number 11,835,573
- Issue date Dec 5, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Interposer circuit
- Patent number 11,835,581
- Issue date Dec 5, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Selectable JTAG or trace access with data store and output
- Patent number 11,835,578
- Issue date Dec 5, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
AT-speed test access port operations
- Patent number 11,808,810
- Issue date Nov 7, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Wafer scale testing using a 2 signal JTAG interface
- Patent number 11,782,091
- Issue date Oct 10, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Integrated circuit with reduced signaling interface
- Patent number 11,768,238
- Issue date Sep 26, 2023
- Texas Instruments Incorporated
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
DEVICE ACCESS PORT SELECTION
- Publication number 20250155502
- Publication date May 15, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
AT-SPEED TEST ACCESS PORT OPERATIONS
- Publication number 20250130278
- Publication date Apr 24, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20250102569
- Publication date Mar 27, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
THROUGH-SILICON VIA (TSV) TESTING
- Publication number 20250093404
- Publication date Mar 20, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SCAN TESTABLE THROUGH SILICON VIAS
- Publication number 20250087539
- Publication date Mar 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
COMMANDED JTAG TEST ACCESS PORT OPERATIONS
- Publication number 20250085343
- Publication date Mar 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES
- Publication number 20250052811
- Publication date Feb 13, 2025
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
- Publication number 20240402247
- Publication date Dec 5, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
ADDRESSABLE TEST ACCESS PORT
- Publication number 20240385244
- Publication date Nov 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
- Publication number 20240345154
- Publication date Oct 17, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER
- Publication number 20240337691
- Publication date Oct 10, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20240319274
- Publication date Sep 26, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT
- Publication number 20240264230
- Publication date Aug 8, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
MULTIPLE ACCESS PORT CIRCUITS
- Publication number 20240183903
- Publication date Jun 6, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
INTERPOSER INSTRUMENTATION METHOD AND APPARATUS
- Publication number 20240133947
- Publication date Apr 25, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TSV TESTING
- Publication number 20240094280
- Publication date Mar 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTERPOSER CIRCUIT
- Publication number 20240094289
- Publication date Mar 21, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
AT-SPEED TEST ACCESS PORT OPERATIONS
- Publication number 20240061038
- Publication date Feb 22, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT
- Publication number 20240019489
- Publication date Jan 18, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS
- Publication number 20240012050
- Publication date Jan 11, 2024
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
3D TAP & SCAN PORT ARCHITECTURES
- Publication number 20230417831
- Publication date Dec 28, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
ADDRESSABLE TEST ACCESS PORT
- Publication number 20230400513
- Publication date Dec 14, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS
- Publication number 20230384376
- Publication date Nov 30, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
INTEGRATED CIRCUIT DIE TEST ARCHITECTURE
- Publication number 20230366920
- Publication date Nov 16, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
FALLING CLOCK EDGE JTAG BUS ROUTERS
- Publication number 20230333163
- Publication date Oct 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY
- Publication number 20230333159
- Publication date Oct 19, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
3D STACKED DIE TEST ARCHITECTURE
- Publication number 20230324812
- Publication date Oct 12, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G03 - PHOTOGRAPHY CINEMATOGRAPHY ELECTROGRAPHY HOLOGRAPHY
Information Patent Application
DEVICE ACCESS PORT SELECTION
- Publication number 20230296670
- Publication date Sep 21, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING
Information Patent Application
TESTING INTERPOSER METHOD AND APPARATUS
- Publication number 20230273238
- Publication date Aug 31, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- B05 - SPRAYING OR ATOMISING IN GENERAL APPLYING LIQUIDS OR OTHER FLUENT MATER...
Information Patent Application
Array of Through-Silicon Via Contact Points on a Semiconductor Die
- Publication number 20230273258
- Publication date Aug 31, 2023
- TEXAS INSTRUMENTS INCORPORATED
- Lee D. Whetsel
- G01 - MEASURING TESTING

Lee D. Whetsel

Person

Patents Grantslast 30 patents

Interposer circuit

Integrated circuit die test architecture

Device access port selection

Test access port with address and command capability

At-speed test access port operations

3D tap and scan port architectures

TSV testing

Scan testable through silicon VIAs

Commanded JTAG test access port operations

Selectable JTAG or trace access with data store and output

Interface to full and reduced pin JTAG devices

Scan frame based test access mechanisms

Selectable JTAG or trace access with data store and output

Addressable test access port

Integrated circuit die test architecture

Programmable test compression architecture input/output shift regis...

3D stacked die test architecture

Test compression in a JTAG daisy-chain environment

Shadow access port method and apparatus

Scan testing using scan frames with embedded commands

Reduced signaling interface method and apparatus

Interposer instrumentation method and apparatus

Two pin serial bus communication interface and process

Device testing architecture, method, and system

TSV testing method and apparatus

Interposer circuit

Selectable JTAG or trace access with data store and output

AT-speed test access port operations

Wafer scale testing using a 2 signal JTAG interface

Integrated circuit with reduced signaling interface

Patents Applicationslast 30 patents

DEVICE ACCESS PORT SELECTION

AT-SPEED TEST ACCESS PORT OPERATIONS

3D TAP & SCAN PORT ARCHITECTURES

THROUGH-SILICON VIA (TSV) TESTING

SCAN TESTABLE THROUGH SILICON VIAS

COMMANDED JTAG TEST ACCESS PORT OPERATIONS

INTERFACE TO FULL AND REDUCED PIN JTAG DEVICES

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

ADDRESSABLE TEST ACCESS PORT

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

PROGRAMMABLE TEST COMPRESSION ARCHITECTURE INPUT/OUTPUT SHIFT REGISTER

3D STACKED DIE TEST ARCHITECTURE

TEST COMPRESSION IN A JTAG DAISY-CHAIN ENVIRONMENT

MULTIPLE ACCESS PORT CIRCUITS

INTERPOSER INSTRUMENTATION METHOD AND APPARATUS

TSV TESTING

INTERPOSER CIRCUIT

AT-SPEED TEST ACCESS PORT OPERATIONS

SELECTABLE JTAG OR TRACE ACCESS WITH DATA STORE AND OUTPUT

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

3D TAP & SCAN PORT ARCHITECTURES

ADDRESSABLE TEST ACCESS PORT

SCAN TESTING USING SCAN FRAMES WITH EMBEDDED COMMANDS

INTEGRATED CIRCUIT DIE TEST ARCHITECTURE

FALLING CLOCK EDGE JTAG BUS ROUTERS

TEST ACCESS PORT WITH ADDRESS AND COMMAND CAPABILITY

3D STACKED DIE TEST ARCHITECTURE

DEVICE ACCESS PORT SELECTION

TESTING INTERPOSER METHOD AND APPARATUS

Array of Through-Silicon Via Contact Points on a Semiconductor Die