Leelean Shu

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Los Altos, CA, US

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Patents Grantslast 30 patents

Information Patent Grant
In-memory full adder
- Patent number 11,604,850
- Issue date Mar 14, 2023
- GSI Technology Inc.
- LeeLean Shu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Four steps associative full adder
- Patent number 10,534,836
- Issue date Jan 14, 2020
- GSI Technology Inc.
- LeeLean Shu
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Systems and methods of double/quad data rate memory involving input...
- Patent number 9,484,076
- Issue date Nov 1, 2016
- GSI Technology, Inc.
- Leelean Shu
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods of memory and memory operation involving input...
- Patent number 9,431,079
- Issue date Aug 30, 2016
- GSI Technology, Inc.
- Leelean Shu
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods of double/quad data rate memory involving input...
- Patent number 9,159,391
- Issue date Oct 13, 2015
- GSI Technology, Inc.
- Leelean Shu
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods of sectioned bit line memory arrays, including...
- Patent number 8,693,236
- Issue date Apr 8, 2014
- GSI Technology, Inc.
- LeeLean Shu
- G11 - INFORMATION STORAGE
Information Patent Grant
Systems and methods of sectioned bit line memory arrays
- Patent number 8,593,860
- Issue date Nov 26, 2013
- GSI Technology, Inc.
- LeeLean Shu
- G11 - INFORMATION STORAGE

Patents Applicationslast 30 patents

Information Patent Application
NON-DESTRUCTIVE MEMORY ARRAY TO IMPLEMENT A FULL ADDER
- Publication number 20200151236
- Publication date May 14, 2020
- GSI Technology Inc.
- LeeLean SHU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
FOUR STEPS ASSOCIATIVE FULL ADDER
- Publication number 20180157621
- Publication date Jun 7, 2018
- GSI Technology Inc.
- LeeLean SHU
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
SYSTEMS AND METHODS OF SECTIONED BIT LINE MEMORY ARRAYS, INCLUDING...
- Publication number 20130148415
- Publication date Jun 13, 2013
- LeeLean Shu
- G11 - INFORMATION STORAGE
Information Patent Application
SYSTEMS AND METHODS OF SECTIONED BIT LINE MEMORY ARRAYS
- Publication number 20130148414
- Publication date Jun 13, 2013
- LeeLean Shu
- G11 - INFORMATION STORAGE