Leendert M. Huisman

Person

South Burlington, VT, US

People

Patents Grantslast 30 patents

Information Patent Grant
Scan chain diagnostics using logic paths
- Patent number 7,895,487
- Issue date Feb 22, 2011
- International Business Machines Corporation
- Leendert M. Huisman
- G11 - INFORMATION STORAGE
Information Patent Grant
Methods and apparatus for testing a scan chain to isolate defects
- Patent number 7,752,514
- Issue date Jul 6, 2010
- International Business Machines Corporation
- Leendert M. Huisman
- G01 - MEASURING TESTING
Information Patent Grant
Learning based logic diagnosis
- Patent number 7,558,999
- Issue date Jul 7, 2009
- International Business Machines Corporation
- James W. Adkisson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using clock gating or signal gating to partition a device for fault...
- Patent number 7,434,130
- Issue date Oct 7, 2008
- International Business Machines Corporation
- Leendert M. Huisman
- G01 - MEASURING TESTING
Information Patent Grant
Methods and apparatus for testing a scan chain to isolate defects
- Patent number 7,313,744
- Issue date Dec 25, 2007
- International Business Machines Corporation
- Leendert M. Huisman
- G01 - MEASURING TESTING
Information Patent Grant
Scan chain diagnostics using logic paths
- Patent number 7,240,261
- Issue date Jul 3, 2007
- International Business Machines Corporation
- Leendert M. Huisman
- G11 - INFORMATION STORAGE
Information Patent Grant
Inspection methods and structures for visualizing and/or detecting...
- Patent number 7,230,335
- Issue date Jun 12, 2007
- International Business Machines Corporation
- Jerome L. Cann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Designing scan chains with specific parameter sensitivities to iden...
- Patent number 7,194,706
- Issue date Mar 20, 2007
- International Business Machines Corporation
- James W. Adkisson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Segmented scan chains with dynamic reconfigurations
- Patent number 7,139,950
- Issue date Nov 21, 2006
- International Business Machines Corporation
- Leendert M. Huisman
- G01 - MEASURING TESTING
Information Patent Grant
Defect diagnosis for semiconductor integrated circuits
- Patent number 7,089,514
- Issue date Aug 8, 2006
- International Business Machines Corporation
- James W. Adkisson
- G01 - MEASURING TESTING
Information Patent Grant
Methodology for fixing Qcrit at design timing impact
- Patent number 6,954,916
- Issue date Oct 11, 2005
- International Business Machines Corporation
- Kerry Bernstein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Rapid fail analysis of embedded objects
- Patent number 6,931,580
- Issue date Aug 16, 2005
- International Business Machines Corporation
- Kevin J. Barcomb
- G11 - INFORMATION STORAGE
Information Patent Grant
Internal cache for on chip test data storage
- Patent number 6,901,542
- Issue date May 31, 2005
- International Business Machines Corporation
- Thomas W. Bartenstein
- G11 - INFORMATION STORAGE
Information Patent Grant
Method to detect systematic defects in VLSI manufacturing
- Patent number 6,880,136
- Issue date Apr 12, 2005
- International Business Machines Corporation
- Leendert M. Huisman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Using clock gating or signal gating to partition a device for fault...
- Patent number 6,865,501
- Issue date Mar 8, 2005
- International Business Machines Corporation
- Leendert M. Huisman
- G01 - MEASURING TESTING
Information Patent Grant
Rapid defect analysis by placement of tester fail data
- Patent number 6,785,413
- Issue date Aug 31, 2004
- International Business Machines Corporation
- Kevin J. Barcomb
- G01 - MEASURING TESTING
Information Patent Grant
Diagnosis of combinational logic circuit failures
- Patent number 6,721,914
- Issue date Apr 13, 2004
- International Business Machines Corporation
- Thomas W. Bartenstein
- G01 - MEASURING TESTING
Information Patent Grant
Incremental fault dictionary
- Patent number 6,675,323
- Issue date Jan 6, 2004
- International Business Machines Corporation
- Thomas W. Bartenstein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Using clock gating or signal gating to partition a device for fault...
- Patent number 6,671,644
- Issue date Dec 30, 2003
- International Business Machines Corporation
- Leendert M. Huisman
- G01 - MEASURING TESTING
Information Patent Grant
Diagnosis of RAMS using functional patterns
- Patent number 6,519,725
- Issue date Feb 11, 2003
- International Business Machines Corporation
- Leendert M. Huisman
- G11 - INFORMATION STORAGE
Information Patent Grant
Fault simulation using dynamically alterable behavioral models
- Patent number 6,170,078
- Issue date Jan 2, 2001
- International Business Machines Corporation
- Mark A. Erle
- G01 - MEASURING TESTING
Information Patent Grant
Method for identifying long paths in integrated circuits
- Patent number 6,125,461
- Issue date Sep 26, 2000
- International Business Machines Corporation
- Leendert Marinus Huisman
- G01 - MEASURING TESTING
Information Patent Grant
Adjustable weighted random test pattern generator for logic circuits
- Patent number 5,297,151
- Issue date Mar 22, 1994
- International Business Machines Corporation
- Matthias Gruetzner
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Grant
Determination of testability of combined logic end memory by ignori...
- Patent number 4,726,023
- Issue date Feb 16, 1988
- International Business Machines Corporation
- John L. Carter
- G06 - COMPUTING CALCULATING COUNTING

Patents Applicationslast 30 patents

Information Patent Application
USING CLOCK GATING OR SIGNAL GATING TO PARTITION A DEVICE FOR FAULT...
- Publication number 20080098268
- Publication date Apr 24, 2008
- IBM
- Leendert M. Huisman
- G01 - MEASURING TESTING
Information Patent Application
METHODS AND APPARATUS FOR TESTING A SCAN CHAIN TO ISOLATE DEFECTS
- Publication number 20080059857
- Publication date Mar 6, 2008
- IBM
- LEENDERT M. HUISMAN
- G01 - MEASURING TESTING
Information Patent Application
SCAN CHAIN DIAGNOSTICS USING LOGIC PATHS
- Publication number 20070168805
- Publication date Jul 19, 2007
- Leendert M. Huisman
- G01 - MEASURING TESTING
Information Patent Application
INSPECTION METHODS AND STRUCTURES FOR VISUALIZING AND/OR DETECTING...
- Publication number 20060071208
- Publication date Apr 6, 2006
- International Business Machines Corporation
- Jerome L. Cann
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
DEFECT DIAGNOSIS FOR SEMICONDUCTOR INTEGRATED CIRCUITS
- Publication number 20060036975
- Publication date Feb 16, 2006
- International Business Machines Corporation
- James W. Adkisson
- G01 - MEASURING TESTING
Information Patent Application
Designing Scan Chains With Specific Parameter Sensitivities to Iden...
- Publication number 20060026472
- Publication date Feb 2, 2006
- International Business Machines Corporation
- James W. Adkisson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
LEARNING BASED LOGIC DIAGNOSIS
- Publication number 20050273656
- Publication date Dec 8, 2005
- International Business Machines Corporation
- James W. Adkisson
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
METHODS AND APPARATUS FOR DEFECT ISOLATION
- Publication number 20050193297
- Publication date Sep 1, 2005
- International Business Machines Corporation
- Leendert M. Huisman
- G01 - MEASURING TESTING
Information Patent Application
SEGMENTED SCAN CHAINS WITH DYNAMIC RECONFIGURATIONS
- Publication number 20050166108
- Publication date Jul 28, 2005
- International Business Machines Corporation
- Leendert M. Huisman
- G01 - MEASURING TESTING
Information Patent Application
SCAN CHAIN DIAGNOSTICS USING LOGIC PATHS
- Publication number 20050138508
- Publication date Jun 23, 2005
- International Business Machines Corporation
- Leendert M. Huisman
- G01 - MEASURING TESTING
Information Patent Application
Using clock gating or signal gating to partition a device for fault...
- Publication number 20050108599
- Publication date May 19, 2005
- IBM
- Leendert M. Huisman
- G01 - MEASURING TESTING
Information Patent Application
METHODOLOGY FOR FIXING Qcrit AT DESIGN TIMING IMPACT
- Publication number 20040267514
- Publication date Dec 30, 2004
- International Business Machines Corporation
- Kerry Bernstein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Using clock gating or signal gating to partition a device for fault...
- Publication number 20040093185
- Publication date May 13, 2004
- International Business Machines Corporation
- Leendert M. Huisman
- G01 - MEASURING TESTING
Information Patent Application
Method to detect systematic defects in VLSI manufacturing
- Publication number 20040009616
- Publication date Jan 15, 2004
- International Business Machines Corporation
- Leendert M. Huisman
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Incremental fault dictionary
- Publication number 20030046608
- Publication date Mar 6, 2003
- Thomas W. Bartenstein
- G06 - COMPUTING CALCULATING COUNTING
Information Patent Application
Using clock gating or signal gating to partition a device for fault...
- Publication number 20030036869
- Publication date Feb 20, 2003
- International Business Machines Corporation
- Leendert M. Huisman
- G01 - MEASURING TESTING
Information Patent Application
Internal cache for on chip test data storage
- Publication number 20030033566
- Publication date Feb 13, 2003
- International Business Machines Corporation
- Thomas W. Bartenstein
- G11 - INFORMATION STORAGE
Information Patent Application
Diagnosis of combinational logic circuit failures
- Publication number 20020147952
- Publication date Oct 10, 2002
- International Business Machines Corporation
- Thomas W. Bartenstein
- G01 - MEASURING TESTING

Leendert M. Huisman

Person

Patents Grantslast 30 patents

Scan chain diagnostics using logic paths

Methods and apparatus for testing a scan chain to isolate defects

Learning based logic diagnosis

Using clock gating or signal gating to partition a device for fault...

Methods and apparatus for testing a scan chain to isolate defects

Scan chain diagnostics using logic paths

Inspection methods and structures for visualizing and/or detecting...

Designing scan chains with specific parameter sensitivities to iden...

Segmented scan chains with dynamic reconfigurations

Defect diagnosis for semiconductor integrated circuits

Methodology for fixing Qcrit at design timing impact

Rapid fail analysis of embedded objects

Internal cache for on chip test data storage

Method to detect systematic defects in VLSI manufacturing

Using clock gating or signal gating to partition a device for fault...

Rapid defect analysis by placement of tester fail data

Diagnosis of combinational logic circuit failures

Incremental fault dictionary

Using clock gating or signal gating to partition a device for fault...

Diagnosis of RAMS using functional patterns

Fault simulation using dynamically alterable behavioral models

Method for identifying long paths in integrated circuits

Adjustable weighted random test pattern generator for logic circuits

Determination of testability of combined logic end memory by ignori...

Patents Applicationslast 30 patents

USING CLOCK GATING OR SIGNAL GATING TO PARTITION A DEVICE FOR FAULT...

METHODS AND APPARATUS FOR TESTING A SCAN CHAIN TO ISOLATE DEFECTS

SCAN CHAIN DIAGNOSTICS USING LOGIC PATHS

INSPECTION METHODS AND STRUCTURES FOR VISUALIZING AND/OR DETECTING...

DEFECT DIAGNOSIS FOR SEMICONDUCTOR INTEGRATED CIRCUITS

Designing Scan Chains With Specific Parameter Sensitivities to Iden...

LEARNING BASED LOGIC DIAGNOSIS

METHODS AND APPARATUS FOR DEFECT ISOLATION

SEGMENTED SCAN CHAINS WITH DYNAMIC RECONFIGURATIONS

SCAN CHAIN DIAGNOSTICS USING LOGIC PATHS

Using clock gating or signal gating to partition a device for fault...

METHODOLOGY FOR FIXING Qcrit AT DESIGN TIMING IMPACT

Using clock gating or signal gating to partition a device for fault...

Method to detect systematic defects in VLSI manufacturing

Incremental fault dictionary

Using clock gating or signal gating to partition a device for fault...

Internal cache for on chip test data storage

Diagnosis of combinational logic circuit failures