Lei Xue

Person

Saratoga, CA, US

People

Patents Grantslast 30 patents

Information Patent Grant
Non-volatile memory with silicided bit line contacts
- Patent number 11,183,509
- Issue date Nov 23, 2021
- Cypress Semiconductor Corporation
- Ching-Huang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory with silicided bit line contacts
- Patent number 10,692,877
- Issue date Jun 23, 2020
- Cypress Semiconductor Corporation
- Ching-Huang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Split-gate semiconductor device with L-shaped gate
- Patent number 10,593,688
- Issue date Mar 17, 2020
- Cypress Semiconductor Corporation
- Scott A. Bell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned trench isolation in integrated circuits
- Patent number 10,256,137
- Issue date Apr 9, 2019
- Cypress Semiconductor Corporation
- Ching-Huang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory device with multi-layer channel and charge trapping layer
- Patent number 10,020,317
- Issue date Jul 10, 2018
- Cypress Semiconductor Corporation
- Renhua Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Split-gate semiconductor device with L-shaped gate
- Patent number 10,020,316
- Issue date Jul 10, 2018
- Cypress Semiconductor Corporation
- Scott Bell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned trench isolation in integrated circuits
- Patent number 9,831,114
- Issue date Nov 28, 2017
- Cypress Semiconductor Corporation
- Ching-Huang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Non-volatile memory with silicided bit line contacts
- Patent number 9,666,591
- Issue date May 30, 2017
- Cypress Semiconductor Corporation
- Ching-Huang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Split-gate semiconductor device with L-shaped gate
- Patent number 9,589,805
- Issue date Mar 7, 2017
- Cypress Semiconductor Corporation
- Scott Bell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Self-aligned trench isolation in integrated circuits
- Patent number 9,437,470
- Issue date Sep 6, 2016
- Cypress Semiconductor Corporation
- Ching-Huang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrating transistors with different poly-silicon heights on the...
- Patent number 9,431,503
- Issue date Aug 30, 2016
- Cypress Semiconductor Corporation
- Chuan Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
CT-NOR differential bitline sensing architecture
- Patent number 9,362,293
- Issue date Jun 7, 2016
- Cypress Semiconductor Corporation
- Hagop Nazarian
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-volatile memory with silicided bit line contacts
- Patent number 9,252,154
- Issue date Feb 2, 2016
- Cypress Semiconductor Corporation
- Ching-Huang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Buried trench isolation in integrated circuits
- Patent number 9,252,026
- Issue date Feb 2, 2016
- Cypress Semiconductor Corporation
- Rinji Sugino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Oro and orpro with bit line trench to suppress transport program di...
- Patent number 9,245,895
- Issue date Jan 26, 2016
- Cypress Semiconductor Corporation
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Adjacent wordline disturb reduction using boron/indium implant
- Patent number 9,153,596
- Issue date Oct 6, 2015
- Cypress Semiconductor Corporation
- Gulzar A. Kathawala
- G11 - INFORMATION STORAGE
Information Patent Grant
Non-Volatile memory with silicided bit line contacts
- Patent number 8,866,213
- Issue date Oct 21, 2014
- Spansion LLC
- Ching-Huang Lu
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Patterned dummy wafers loading in batch type CVD
- Patent number 8,809,206
- Issue date Aug 19, 2014
- Spansion LLC
- Rinji Sugino
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Grant
Memory cell system with multiple nitride layers
- Patent number 8,809,936
- Issue date Aug 19, 2014
- GLOBALFOUNDRIES Inc.
- Lei Xue
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell system using silicon-rich nitride
- Patent number 8,803,216
- Issue date Aug 12, 2014
- Spansion, LLC
- Meng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory system with Fin FET technology
- Patent number 8,785,268
- Issue date Jul 22, 2014
- Spansion LLC
- Wei Zheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Integrating transistors with different poly-silicon heights on the...
- Patent number 8,652,907
- Issue date Feb 18, 2014
- Spansion LLC
- Chuan Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Method and manufacture for embedded flash to achieve high quality s...
- Patent number 8,598,005
- Issue date Dec 3, 2013
- Spansion LLC
- Simon Siu-Sing Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Memory cell system with charge trap
- Patent number 8,587,049
- Issue date Nov 19, 2013
- Spansion, LLC
- Meng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
High read speed memory with gate isolation
- Patent number 8,520,437
- Issue date Aug 27, 2013
- Spansion LLC
- Richard Fastow
- G11 - INFORMATION STORAGE
Information Patent Grant
High read speed memory with gate isolation
- Patent number 8,279,674
- Issue date Oct 2, 2012
- Spansion LLC
- Richard Fastow
- G11 - INFORMATION STORAGE
Information Patent Grant
Memory cell system with charge trap
- Patent number 8,143,661
- Issue date Mar 27, 2012
- Spansion LLC
- Shenqing Fang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
ORO and ORPRO with bit line trench to suppress transport program di...
- Patent number 8,012,830
- Issue date Sep 6, 2011
- Spansion LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
SI trench between bitline HDP for BVDSS improvement
- Patent number 7,951,675
- Issue date May 31, 2011
- Spansion LLC
- Lei Xue
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Grant
Use of a polymer spacer and Si trench in a bitline junction of a fl...
- Patent number 7,906,807
- Issue date Mar 15, 2011
- Spansion LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS

Patents Applicationslast 30 patents

Information Patent Application
Non-Volatile Memory With Silicided Bit Line Contacts
- Publication number 20200411537
- Publication date Dec 31, 2020
- Infineon Technologies LLC
- Ching-Huang LU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buried Trench Isolation in Integrated Circuits
- Publication number 20190198611
- Publication date Jun 27, 2019
- CYPRESS SEMICONDUCTOR CORPORATION
- Rinji Sugino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE
- Publication number 20180358367
- Publication date Dec 13, 2018
- CYPRESS SEMICONDUCTOR CORPORATION
- Scott A. Bell
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL DIVISION OF THREE-DIMENSIONAL MEMORY DEVICE
- Publication number 20180323208
- Publication date Nov 8, 2018
- CYPRESS SEMICONDUCTOR CORPORATION
- Rinji Sugino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED TRENCH ISOLATION IN INTEGRATED CIRCUITS
- Publication number 20180166323
- Publication date Jun 14, 2018
- CYPRESS SEMICONDUCTOR CORPORATION
- Ching-Huang LU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory Device with Multi-Layer Channel and Charge Trapping Layer
- Publication number 20170263623
- Publication date Sep 14, 2017
- CYPRESS SEMICONDUCTOR CORPORATION
- Renhua Zhang
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-Volatile Memory With Silicided Bit Line Contacts
- Publication number 20170250192
- Publication date Aug 31, 2017
- CYPRESS SEMICONDUCTOR CORPORATION
- Ching-Huang LU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE
- Publication number 20170162586
- Publication date Jun 8, 2017
- CYPRESS SEMICONDUCTOR CORPORATION
- Scott BELL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
VERTICAL DIVISION OF THREE-DIMENSIONAL MEMORY DEVICE
- Publication number 20170062456
- Publication date Mar 2, 2017
- CYPRESS SEMICONDUCTOR CORPORATION
- Rinji Sugino
- G11 - INFORMATION STORAGE
Information Patent Application
Non-Volatile Memory With Silicided Bit Line Contacts
- Publication number 20160211271
- Publication date Jul 21, 2016
- CYPRESS SEMICONDUCTOR CORPORATION
- Ching-Huang LU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buried Trench Isolation in Integrated Circuits
- Publication number 20160211321
- Publication date Jul 21, 2016
- CYPRESS SEMICONDUCTOR CORPORATION
- Rinji Sugino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE
- Publication number 20160035576
- Publication date Feb 4, 2016
- CYPRESS SEMICONDUCTOR CORPORATION
- Scott BELL
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Buried Trench Isolation in Integrated Circuits
- Publication number 20150262838
- Publication date Sep 17, 2015
- SPANSION LLC
- Rinji Sugino
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
CT-NOR DIFFERENTIAL BITLINE SENSING ARCHITECTURE
- Publication number 20150179656
- Publication date Jun 25, 2015
- SPANSION LLC
- Hagop Nazarian
- G11 - INFORMATION STORAGE
Information Patent Application
BURIED TRENCH ISOLATION IN INTEGRATED CIRCUITS
- Publication number 20150097224
- Publication date Apr 9, 2015
- SPANSION LLC
- Lei XUE
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
SELF-ALIGNED TRENCH ISOLATION IN INTEGRATED CIRCUITS
- Publication number 20150097245
- Publication date Apr 9, 2015
- SPANSION LLC
- Ching-Huang LU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-Volatile Memory With Silicided Bit Line Contacts
- Publication number 20150017795
- Publication date Jan 15, 2015
- SPANSION LLC
- Ching-Huang LU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Non-Volatile Memory With Silicided Bit Line Contacts
- Publication number 20140209993
- Publication date Jul 31, 2014
- SPANSION LLC
- Ching-Huang LU
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE...
- Publication number 20140117435
- Publication date May 1, 2014
- SPANSION LLC
- Chuan LIN
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
Memory Device with Charge Trap
- Publication number 20140061771
- Publication date Mar 6, 2014
- SPANSION, LLC
- Meng Ding
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
METHOD AND MANUFACTURE FOR EMBEDDED FLASH TO ACHIEVE HIGH QUALITY S...
- Publication number 20130023101
- Publication date Jan 24, 2013
- SPANSION LLC
- Simon Siu-Sing Chan
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
HIGH READ SPEED MEMORY WITH GATE ISOLATION
- Publication number 20120327717
- Publication date Dec 27, 2012
- SPANSION LLC
- Richard Fastow
- G11 - INFORMATION STORAGE
Information Patent Application
INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE...
- Publication number 20120241871
- Publication date Sep 27, 2012
- SPANSION LLC
- Chuan Lin
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
PATTERNED DUMMY WAFERS LOADING IN BATCH TYPE CVD
- Publication number 20120202355
- Publication date Aug 9, 2012
- SPANSION LLC
- Rinji Sugino
- C23 - COATING METALLIC MATERIAL COATING MATERIAL WITH METALLIC MATERIAL CHEMI...
Information Patent Application
HIGH READ SPEED MEMORY WITH GATE ISOLATION
- Publication number 20110317466
- Publication date Dec 29, 2011
- SPANSION LLC
- Richard Fastow
- G11 - INFORMATION STORAGE
Information Patent Application
ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DI...
- Publication number 20110278660
- Publication date Nov 17, 2011
- SPANSION LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FL...
- Publication number 20100264480
- Publication date Oct 21, 2010
- SPANSION LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
ADJACENT WORDLINE DISTURB REDUCTION USING BORON/INDIUM IMPLANT
- Publication number 20100213535
- Publication date Aug 26, 2010
- SPANSION LLC
- Gulzar A. Kathawala
- G11 - INFORMATION STORAGE
Information Patent Application
SI TRENCH BETWEEN BITLINE HDP FOR BVDSS IMPROVEMENT
- Publication number 20090152669
- Publication date Jun 18, 2009
- SPANSION LLC
- Lei Xue
- H01 - BASIC ELECTRIC ELEMENTS
Information Patent Application
USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FL...
- Publication number 20090042378
- Publication date Feb 12, 2009
- SPANSION LLC
- Ning Cheng
- H01 - BASIC ELECTRIC ELEMENTS

Person

Patents Grantslast 30 patents

Non-volatile memory with silicided bit line contacts

Non-volatile memory with silicided bit line contacts

Split-gate semiconductor device with L-shaped gate

Self-aligned trench isolation in integrated circuits

Memory device with multi-layer channel and charge trapping layer

Split-gate semiconductor device with L-shaped gate

Self-aligned trench isolation in integrated circuits

Non-volatile memory with silicided bit line contacts

Split-gate semiconductor device with L-shaped gate

Self-aligned trench isolation in integrated circuits

Integrating transistors with different poly-silicon heights on the...

CT-NOR differential bitline sensing architecture

Non-volatile memory with silicided bit line contacts

Buried trench isolation in integrated circuits

Oro and orpro with bit line trench to suppress transport program di...

Adjacent wordline disturb reduction using boron/indium implant

Non-Volatile memory with silicided bit line contacts

Patterned dummy wafers loading in batch type CVD

Memory cell system with multiple nitride layers

Memory cell system using silicon-rich nitride

Memory system with Fin FET technology

Integrating transistors with different poly-silicon heights on the...

Method and manufacture for embedded flash to achieve high quality s...

Memory cell system with charge trap

High read speed memory with gate isolation

High read speed memory with gate isolation

Memory cell system with charge trap

ORO and ORPRO with bit line trench to suppress transport program di...

SI trench between bitline HDP for BVDSS improvement

Use of a polymer spacer and Si trench in a bitline junction of a fl...

Patents Applicationslast 30 patents

Non-Volatile Memory With Silicided Bit Line Contacts

Buried Trench Isolation in Integrated Circuits

SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE

VERTICAL DIVISION OF THREE-DIMENSIONAL MEMORY DEVICE

SELF-ALIGNED TRENCH ISOLATION IN INTEGRATED CIRCUITS

Memory Device with Multi-Layer Channel and Charge Trapping Layer

Non-Volatile Memory With Silicided Bit Line Contacts

SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE

VERTICAL DIVISION OF THREE-DIMENSIONAL MEMORY DEVICE

Non-Volatile Memory With Silicided Bit Line Contacts

Buried Trench Isolation in Integrated Circuits

SPLIT-GATE SEMICONDUCTOR DEVICE WITH L-SHAPED GATE

Buried Trench Isolation in Integrated Circuits

CT-NOR DIFFERENTIAL BITLINE SENSING ARCHITECTURE

BURIED TRENCH ISOLATION IN INTEGRATED CIRCUITS

SELF-ALIGNED TRENCH ISOLATION IN INTEGRATED CIRCUITS

Non-Volatile Memory With Silicided Bit Line Contacts

Non-Volatile Memory With Silicided Bit Line Contacts

INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE...

Memory Device with Charge Trap

METHOD AND MANUFACTURE FOR EMBEDDED FLASH TO ACHIEVE HIGH QUALITY S...

HIGH READ SPEED MEMORY WITH GATE ISOLATION

INTEGRATING TRANSISTORS WITH DIFFERENT POLY-SILICON HEIGHTS ON THE...

PATTERNED DUMMY WAFERS LOADING IN BATCH TYPE CVD

HIGH READ SPEED MEMORY WITH GATE ISOLATION

ORO AND ORPRO WITH BIT LINE TRENCH TO SUPPRESS TRANSPORT PROGRAM DI...

USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FL...

ADJACENT WORDLINE DISTURB REDUCTION USING BORON/INDIUM IMPLANT

SI TRENCH BETWEEN BITLINE HDP FOR BVDSS IMPROVEMENT

USE OF A POLYMER SPACER AND SI TRENCH IN A BITLINE JUNCTION OF A FL...